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[mips] Set flag neverHasSideEffects flag on floating point conversion

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instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167348 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2012-11-03 00:53:12 +00:00
parent b4b04c3fa0
commit 3c77033a90
3 changed files with 27 additions and 6 deletions
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13
lib/Target/Mips/MipsInstrFPU.td
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@ -182,20 +182,21 @@ defm CEIL_W : FFR1_W_M<0xe, "ceil">;
defm CEIL_L : FFR1_L_M<0xa, "ceil">;
defm FLOOR_W : FFR1_W_M<0xf, "floor">;
defm FLOOR_L : FFR1_L_M<0xb, "floor">;
defm CVT_W : FFR1_W_M<0x24, "cvt">;
defm CVT_W : FFR1_W_M<0x24, "cvt">, NeverHasSideEffects;
//defm CVT_L : FFR1_L_M<0x25, "cvt">;
def CVT_S_W : FFR1<0x20, 20, "cvt", "s.w", FGR32, FGR32>;
def CVT_L_S : FFR1<0x25, 16, "cvt", "l.s", FGR64, FGR32>;
def CVT_L_D64: FFR1<0x25, 17, "cvt", "l.d", FGR64, FGR64>;
def CVT_S_W : FFR1<0x20, 20, "cvt", "s.w", FGR32, FGR32>, NeverHasSideEffects;
def CVT_L_S : FFR1<0x25, 16, "cvt", "l.s", FGR64, FGR32>, NeverHasSideEffects;
def CVT_L_D64: FFR1<0x25, 17, "cvt", "l.d", FGR64, FGR64>, NeverHasSideEffects;
let Predicates = [NotFP64bit, HasStandardEncoding] in {
let Predicates = [NotFP64bit, HasStandardEncoding], neverHasSideEffects = 1 in {
def CVT_S_D32 : FFR1<0x20, 17, "cvt", "s.d", FGR32, AFGR64>;
def CVT_D32_W : FFR1<0x21, 20, "cvt", "d.w", AFGR64, FGR32>;
def CVT_D32_S : FFR1<0x21, 16, "cvt", "d.s", AFGR64, FGR32>;
}
let Predicates = [IsFP64bit, HasStandardEncoding], DecoderNamespace = "Mips64" in {
let Predicates = [IsFP64bit, HasStandardEncoding], DecoderNamespace = "Mips64",
neverHasSideEffects = 1 in {
def CVT_S_D64 : FFR1<0x20, 17, "cvt", "s.d", FGR32, FGR64>;
def CVT_S_L : FFR1<0x20, 21, "cvt", "s.l", FGR32, FGR64>;
def CVT_D64_W : FFR1<0x21, 20, "cvt", "d.w", FGR64, FGR32>;

4
lib/Target/Mips/MipsInstrInfo.td
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@ -204,6 +204,10 @@ class IsAsCheapAsAMove {
bit isAsCheapAsAMove = 1;
}
class NeverHasSideEffects {
bit neverHasSideEffects = 1;
}
//===----------------------------------------------------------------------===//
// Instruction format superclass
//===----------------------------------------------------------------------===//

16
test/CodeGen/Mips/brdelayslot.ll
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@ -19,3 +19,19 @@ entry:
}
declare void @foo2(i32)
; Check that cvt.d.w goes into jalr's delay slot.
;
define void @foo3(i32 %a) nounwind {
entry:
; Default: foo3:
; Default: jalr
; Default: cvt.d.w
%conv = sitofp i32 %a to double
tail call void @foo4(double %conv) nounwind
ret void
}
declare void @foo4(double)