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https://github.com/c64scene-ar/llvm-6502.git
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Implement NEON domain switching for scalar <-> S-register vmovs on ARM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162094 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover
parent
734fd27647
commit
3c8ad92455
@ -3354,11 +3354,18 @@ enum ARMExeDomain {
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//
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std::pair<uint16_t, uint16_t>
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ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const {
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// VMOVD is a VFP instruction, but can be changed to NEON if it isn't
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// predicated.
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// VMOVD, VMOVRS and VMOVSR are VFP instructions, but can be changed to NEON
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// if they are not predicated.
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if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI))
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return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON));
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// Cortex-A9 is particularly picky about mixing the two and wants these
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// converted.
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if (Subtarget.isCortexA9() && !isPredicated(MI) &&
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(MI->getOpcode() == ARM::VMOVRS ||
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MI->getOpcode() == ARM::VMOVSR))
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return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON));
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// No other instructions can be swizzled, so just determine their domain.
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unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask;
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@ -3378,22 +3385,97 @@ ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const {
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void
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ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
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// We only know how to change VMOVD into VORR.
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assert(MI->getOpcode() == ARM::VMOVD && "Can only swizzle VMOVD");
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if (Domain != ExeNEON)
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return;
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unsigned DstReg, SrcReg, DReg;
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unsigned Lane;
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MachineInstrBuilder MIB(MI);
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const TargetRegisterInfo *TRI = &getRegisterInfo();
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bool isKill;
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switch (MI->getOpcode()) {
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default:
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llvm_unreachable("cannot handle opcode!");
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break;
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case ARM::VMOVD:
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if (Domain != ExeNEON)
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break;
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// Zap the predicate operands.
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assert(!isPredicated(MI) && "Cannot predicate a VORRd");
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MI->RemoveOperand(3);
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MI->RemoveOperand(2);
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// Zap the predicate operands.
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assert(!isPredicated(MI) && "Cannot predicate a VORRd");
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MI->RemoveOperand(3);
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MI->RemoveOperand(2);
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// Change to a VORRd which requires two identical use operands.
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MI->setDesc(get(ARM::VORRd));
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// Change to a VORRd which requires two identical use operands.
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MI->setDesc(get(ARM::VORRd));
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// Add the extra source operand and new predicates.
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// This will go before any implicit ops.
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AddDefaultPred(MachineInstrBuilder(MI).addOperand(MI->getOperand(1)));
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break;
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case ARM::VMOVRS:
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if (Domain != ExeNEON)
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break;
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assert(!isPredicated(MI) && "Cannot predicate a VGETLN");
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DstReg = MI->getOperand(0).getReg();
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SrcReg = MI->getOperand(1).getReg();
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DReg = TRI->getMatchingSuperReg(SrcReg, ARM::ssub_0, &ARM::DPRRegClass);
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Lane = 0;
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if (DReg == ARM::NoRegister) {
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DReg = TRI->getMatchingSuperReg(SrcReg, ARM::ssub_1, &ARM::DPRRegClass);
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Lane = 1;
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assert(DReg && "S-register with no D super-register?");
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}
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MI->RemoveOperand(3);
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MI->RemoveOperand(2);
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MI->RemoveOperand(1);
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MI->setDesc(get(ARM::VGETLNi32));
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MIB.addReg(DReg);
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MIB.addImm(Lane);
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MIB->getOperand(1).setIsUndef();
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MIB.addReg(SrcReg, RegState::Implicit);
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AddDefaultPred(MIB);
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break;
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case ARM::VMOVSR:
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if (Domain != ExeNEON)
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break;
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assert(!isPredicated(MI) && "Cannot predicate a VSETLN");
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DstReg = MI->getOperand(0).getReg();
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SrcReg = MI->getOperand(1).getReg();
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DReg = TRI->getMatchingSuperReg(DstReg, ARM::ssub_0, &ARM::DPRRegClass);
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Lane = 0;
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if (DReg == ARM::NoRegister) {
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DReg = TRI->getMatchingSuperReg(DstReg, ARM::ssub_1, &ARM::DPRRegClass);
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Lane = 1;
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assert(DReg && "S-register with no D super-register?");
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}
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isKill = MI->getOperand(0).isKill();
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MI->RemoveOperand(3);
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MI->RemoveOperand(2);
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MI->RemoveOperand(1);
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MI->RemoveOperand(0);
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MI->setDesc(get(ARM::VSETLNi32));
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MIB.addReg(DReg);
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MIB.addReg(DReg);
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MIB.addReg(SrcReg);
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MIB.addImm(Lane);
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MIB->getOperand(1).setIsUndef();
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if (isKill)
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MIB->addRegisterKilled(DstReg, TRI, true);
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MIB->addRegisterDefined(DstReg, TRI);
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AddDefaultPred(MIB);
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break;
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}
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// Add the extra source operand and new predicates.
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// This will go before any implicit ops.
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AddDefaultPred(MachineInstrBuilder(MI).addOperand(MI->getOperand(1)));
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}
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bool ARMBaseInstrInfo::hasNOP() const {
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@ -33,16 +33,16 @@ define void @test_cos(<4 x float>* %X) nounwind {
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; CHECK: movt [[reg0]], :upper16:{{.*}}
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; CHECK: vldmia r{{[0-9][0-9]?}}, {{.*}}
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: {{[mov|vmov.32]}} r0,
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; CHECK: bl {{.*}}cosf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: {{[mov|vmov.32]}} r0,
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; CHECK: bl {{.*}}cosf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: {{[mov|vmov.32]}} r0,
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; CHECK: bl {{.*}}cosf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: {{[mov|vmov.32]}} r0,
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; CHECK: bl {{.*}}cosf
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; CHECK: vstmia {{.*}}
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@ -64,16 +64,16 @@ define void @test_exp(<4 x float>* %X) nounwind {
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; CHECK: movt [[reg0]], :upper16:{{.*}}
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; CHECK: vldmia r{{[0-9][0-9]?}}, {{.*}}
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: {{[mov|vmov.32]}} r0,
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; CHECK: bl {{.*}}expf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: {{[mov|vmov.32]}} r0,
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; CHECK: bl {{.*}}expf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: {{[mov|vmov.32]}} r0,
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; CHECK: bl {{.*}}expf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: {{[mov|vmov.32]}} r0,
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; CHECK: bl {{.*}}expf
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; CHECK: vstmia {{.*}}
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@ -95,16 +95,16 @@ define void @test_exp2(<4 x float>* %X) nounwind {
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; CHECK: movt [[reg0]], :upper16:{{.*}}
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; CHECK: vldmia r{{[0-9][0-9]?}}, {{.*}}
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: {{[mov|vmov.32]}} r0,
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; CHECK: bl {{.*}}exp2f
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: {{[mov|vmov.32]}} r0,
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; CHECK: bl {{.*}}exp2f
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: {{[mov|vmov.32]}} r0,
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; CHECK: bl {{.*}}exp2f
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: {{[mov|vmov.32]}} r0,
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; CHECK: bl {{.*}}exp2f
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; CHECK: vstmia {{.*}}
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@ -126,16 +126,16 @@ define void @test_log10(<4 x float>* %X) nounwind {
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; CHECK: movt [[reg0]], :upper16:{{.*}}
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; CHECK: vldmia r{{[0-9][0-9]?}}, {{.*}}
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: {{[mov|vmov.32]}} r0,
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; CHECK: bl {{.*}}log10f
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: {{[mov|vmov.32]}} r0,
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; CHECK: bl {{.*}}log10f
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: {{[mov|vmov.32]}} r0,
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; CHECK: bl {{.*}}log10f
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: {{[mov|vmov.32]}} r0,
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; CHECK: bl {{.*}}log10f
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; CHECK: vstmia {{.*}}
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@ -157,16 +157,16 @@ define void @test_log(<4 x float>* %X) nounwind {
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; CHECK: movt [[reg0]], :upper16:{{.*}}
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; CHECK: vldmia r{{[0-9][0-9]?}}, {{.*}}
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: {{[mov|vmov.32]}} r0,
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; CHECK: bl {{.*}}logf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: {{[mov|vmov.32]}} r0,
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; CHECK: bl {{.*}}logf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: {{[mov|vmov.32]}} r0,
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; CHECK: bl {{.*}}logf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: {{[mov|vmov.32]}} r0,
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; CHECK: bl {{.*}}logf
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; CHECK: vstmia {{.*}}
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@ -188,16 +188,16 @@ define void @test_log2(<4 x float>* %X) nounwind {
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; CHECK: movt [[reg0]], :upper16:{{.*}}
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; CHECK: vldmia r{{[0-9][0-9]?}}, {{.*}}
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: {{[mov|vmov.32]}} r0,
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; CHECK: bl {{.*}}log2f
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: {{[mov|vmov.32]}} r0,
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; CHECK: bl {{.*}}log2f
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: {{[mov|vmov.32]}} r0,
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; CHECK: bl {{.*}}log2f
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: {{[mov|vmov.32]}} r0,
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; CHECK: bl {{.*}}log2f
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; CHECK: vstmia {{.*}}
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@ -220,16 +220,16 @@ define void @test_pow(<4 x float>* %X) nounwind {
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; CHECK: movt [[reg0]], :upper16:{{.*}}
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; CHECK: vldmia r{{[0-9][0-9]?}}, {{.*}}
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: {{[mov|vmov.32]}} r0,
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; CHECK: bl {{.*}}powf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: {{[mov|vmov.32]}} r0,
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; CHECK: bl {{.*}}powf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: {{[mov|vmov.32]}} r0,
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; CHECK: bl {{.*}}powf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: {{[mov|vmov.32]}} r0,
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; CHECK: bl {{.*}}powf
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; CHECK: vstmia {{.*}}
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@ -277,16 +277,16 @@ define void @test_sin(<4 x float>* %X) nounwind {
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; CHECK: movt [[reg0]], :upper16:{{.*}}
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; CHECK: vldmia r{{[0-9][0-9]?}}, {{.*}}
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: {{[mov|vmov.32]}} r0,
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; CHECK: bl {{.*}}sinf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: {{[mov|vmov.32]}} r0,
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; CHECK: bl {{.*}}sinf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: {{[mov|vmov.32]}} r0,
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; CHECK: bl {{.*}}sinf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: {{[mov|vmov.32]}} r0,
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; CHECK: bl {{.*}}sinf
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; CHECK: vstmia {{.*}}
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