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clo/clz aren't supported on mips I. Keep them around for when we'll
want them later (mips32/64). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43380 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher
parent
ef15029258
commit
3c999a270e
@ -2,7 +2,7 @@
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Bruno Cardoso Lopes and is distributed under the
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// This file was developed by Bruno Cardoso Lopes and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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@ -22,31 +22,31 @@ def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
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def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, [SDNPHasChain,
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SDNPOutFlag]>;
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// Hi and Lo nodes are created to let easy manipulation of 16-bit when
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// handling 32-bit immediates. They are used on MipsISelLowering to
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// Hi and Lo nodes are created to let easy manipulation of 16-bit when
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// handling 32-bit immediates. They are used on MipsISelLowering to
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// lower stuff like GlobalAddress, ExternalSymbol, ... on static model
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// This two nodes have nothing to do with Mips Registers Hi and Lo.
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def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp, [SDNPOutFlag]>;
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def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
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def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
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// Necessary to generate glued instructions when loading GlobalAddress
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// into registers.
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def MipsAdd : SDNode<"MipsISD::Add", SDTIntBinOp, [SDNPCommutative,
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def MipsAdd : SDNode<"MipsISD::Add", SDTIntBinOp, [SDNPCommutative,
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SDNPAssociative, SDNPOptInFlag]>;
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// Used to Load Addresses on PIC code.
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def MipsLoadAddr: SDNode<"MipsISD::LoadAddr", SDTIntUnaryOp>;
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// Return
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def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
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def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain,
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// Return
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def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
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def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain,
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SDNPOptInFlag]>;
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// These are target-independent nodes, but have target-specific formats.
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def SDT_MipsCallSeq : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
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def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeq,
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def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeq,
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[SDNPHasChain, SDNPOutFlag]>;
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def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeq,
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def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeq,
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[SDNPHasChain, SDNPOutFlag]>;
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//===----------------------------------------------------------------------===//
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@ -63,7 +63,7 @@ def brtarget : Operand<OtherVT>;
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def calltarget : Operand<i32>;
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def uimm16 : Operand<i32>;
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def simm16 : Operand<i32>;
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def shamt : Operand<i32>;
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def shamt : Operand<i32>;
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def addrlabel : Operand<i32>;
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// Address operand
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@ -87,7 +87,7 @@ def HI16 : SDNodeXForm<imm, [{
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def immSExt16 : PatLeaf<(imm), [{
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if (N->getValueType(0) == MVT::i32)
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return (int32_t)N->getValue() == (short)N->getValue();
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else
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else
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return (int64_t)N->getValue() == (short)N->getValue();
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}]>;
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@ -98,7 +98,7 @@ def immSExt16 : PatLeaf<(imm), [{
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def immZExt16 : PatLeaf<(imm), [{
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if (N->getValueType(0) == MVT::i32)
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return (uint32_t)N->getValue() == (unsigned short)N->getValue();
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else
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else
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return (uint64_t)N->getValue() == (unsigned short)N->getValue();
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}], LO16>;
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@ -112,7 +112,7 @@ def immZExt5 : PatLeaf<(imm), [{
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return N->getValue() == ((N->getValue()) & 0x1f) ;
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}]>;
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// Mips Address Mode! SDNode frameindex could possibily be a match
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// Mips Address Mode! SDNode frameindex could possibily be a match
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// since load and store instructions from stack used it.
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def addr : ComplexPattern<i32, 2, "SelectAddr", [frameindex], []>;
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@ -121,52 +121,52 @@ def addr : ComplexPattern<i32, 2, "SelectAddr", [frameindex], []>;
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//===----------------------------------------------------------------------===//
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// Arithmetic 3 register operands
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let isCommutable = 1 in
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let isCommutable = 1 in
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class ArithR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
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InstrItinClass itin>:
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FR< op,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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InstrItinClass itin>:
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FR< op,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], itin>;
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let isCommutable = 1 in
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class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm>:
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FR< op,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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let isCommutable = 1 in
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class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm>:
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FR< op,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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[], IIAlu>;
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// Arithmetic 2 register operands
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let isCommutable = 1 in
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class ArithI<bits<6> op, string instr_asm, SDNode OpNode,
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Operand Od, PatLeaf imm_type> :
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FI< op,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, Od:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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class ArithI<bits<6> op, string instr_asm, SDNode OpNode,
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Operand Od, PatLeaf imm_type> :
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FI< op,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, Od:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, imm_type:$c))], IIAlu>;
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// Arithmetic Multiply ADD/SUB
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let rd=0 in
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class MArithR<bits<6> func, string instr_asm> :
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FR< 0x1c,
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class MArithR<bits<6> func, string instr_asm> :
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FR< 0x1c,
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func,
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(outs CPURegs:$rs),
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(ins CPURegs:$rt),
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!strconcat(instr_asm, " $rs, $rt"),
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(outs CPURegs:$rs),
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(ins CPURegs:$rt),
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!strconcat(instr_asm, " $rs, $rt"),
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[], IIImul>;
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// Logical
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class LogicR<bits<6> func, string instr_asm, SDNode OpNode>:
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FR< 0x00,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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FR< 0x00,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
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class LogicI<bits<6> op, string instr_asm, SDNode OpNode>:
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@ -177,29 +177,29 @@ class LogicI<bits<6> op, string instr_asm, SDNode OpNode>:
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[(set CPURegs:$dst, (OpNode CPURegs:$b, immSExt16:$c))], IIAlu>;
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class LogicNOR<bits<6> op, bits<6> func, string instr_asm>:
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FR< op,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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FR< op,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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[(set CPURegs:$dst, (not (or CPURegs:$b, CPURegs:$c)))], IIAlu>;
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// Shifts
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let rt = 0 in
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class LogicR_shift_imm<bits<6> func, string instr_asm, SDNode OpNode>:
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FR< 0x00,
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func,
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FR< 0x00,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, shamt:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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!strconcat(instr_asm, " $dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt5:$c))], IIAlu>;
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class LogicR_shift_reg<bits<6> func, string instr_asm, SDNode OpNode>:
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FR< 0x00,
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func,
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FR< 0x00,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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!strconcat(instr_asm, " $dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
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// Load Upper Imediate
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@ -210,7 +210,7 @@ class LoadUpper<bits<6> op, string instr_asm>:
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!strconcat(instr_asm, " $dst, $imm"),
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[], IIAlu>;
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// Memory Load/Store
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// Memory Load/Store
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let isLoad = 1, hasDelaySlot = 1 in
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class LoadM<bits<6> op, string instr_asm, PatFrag OpNode>:
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FI< op,
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@ -245,9 +245,9 @@ class CBranchZero<bits<6> op, string instr_asm, PatFrag cond_op>:
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!strconcat(instr_asm, " $src, $offset"),
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[(brcond (cond_op CPURegs:$src, 0), bb:$offset)],
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IIBranch>;
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}
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}
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// SetCC
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// SetCC
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class SetCC_R<bits<6> op, bits<6> func, string instr_asm,
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PatFrag cond_op>:
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FR< op,
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@ -286,11 +286,11 @@ class JumpFR<bits<6> op, bits<6> func, string instr_asm>:
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[], IIBranch>;
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// Jump and Link (Call)
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let isCall=1, hasDelaySlot=1,
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let isCall=1, hasDelaySlot=1,
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// All calls clobber the non-callee saved registers...
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Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2,
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Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2,
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T3, T4, T5, T6, T7, T8, T9, K0, K1] in {
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class JumpLink<bits<6> op, string instr_asm>:
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class JumpLink<bits<6> op, string instr_asm>:
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FJ< op,
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(outs),
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(ins calltarget:$target),
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@ -314,36 +314,36 @@ let isCall=1, hasDelaySlot=1,
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[], IIBranch>;
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}
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// Mul, Div
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class MulDiv<bits<6> func, string instr_asm, InstrItinClass itin>:
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FR< 0x00,
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func,
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// Mul, Div
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class MulDiv<bits<6> func, string instr_asm, InstrItinClass itin>:
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FR< 0x00,
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func,
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(outs),
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(ins CPURegs:$a, CPURegs:$b),
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!strconcat(instr_asm, " $a, $b"),
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(ins CPURegs:$a, CPURegs:$b),
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!strconcat(instr_asm, " $a, $b"),
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[], itin>;
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// Move from Hi/Lo
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// Move from Hi/Lo
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class MoveFromTo<bits<6> func, string instr_asm>:
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FR< 0x00,
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func,
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(outs CPURegs:$dst),
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FR< 0x00,
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func,
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(outs CPURegs:$dst),
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(ins),
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!strconcat(instr_asm, " $dst"),
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!strconcat(instr_asm, " $dst"),
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[], IIHiLo>;
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// Count Leading Ones/Zeros in Word
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class CountLeading<bits<6> func, string instr_asm>:
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FR< 0x1c,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$src),
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!strconcat(instr_asm, " $dst, $src"),
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FR< 0x1c,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$src),
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!strconcat(instr_asm, " $dst, $src"),
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[], IIAlu>;
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class EffectiveAddress<string instr_asm> :
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FI<0x09,
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(outs CPURegs:$dst),
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class EffectiveAddress<string instr_asm> :
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FI<0x09,
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(outs CPURegs:$dst),
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(ins mem:$addr),
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instr_asm,
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[(set CPURegs:$dst, addr:$addr)], IIAlu>;
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@ -366,19 +366,19 @@ def IMPLICIT_DEF_CPURegs : PseudoInstMips<(outs CPURegs:$dst), (ins),
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"!IMPLICIT_DEF $dst",
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[(set CPURegs:$dst, (undef))]>;
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// When handling PIC code the assembler needs .cpload and .cprestore
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// directives. If the real instructions corresponding these directives
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// are used, we have the same behavior, but get also a bunch of warnings
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// When handling PIC code the assembler needs .cpload and .cprestore
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// directives. If the real instructions corresponding these directives
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// are used, we have the same behavior, but get also a bunch of warnings
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// from the assembler.
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def CPLOAD: PseudoInstMips<(outs), (ins CPURegs:$reg),
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def CPLOAD: PseudoInstMips<(outs), (ins CPURegs:$reg),
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".set noreorder\n\t.cpload $reg\n\t.set reorder", []>;
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def CPRESTORE: PseudoInstMips<(outs), (ins uimm16:$loc),
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def CPRESTORE: PseudoInstMips<(outs), (ins uimm16:$loc),
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".cprestore $loc", []>;
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// Used on PIC code only, it loads the address of label into register reg. The
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// address is calculated from the global pointer ($gp) and is expanded by the
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// assembler into two instructions "lw" and "addiu".
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def LA: PseudoInstMips<(outs CPURegs:$dst), (ins addrlabel:$label),
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def LA: PseudoInstMips<(outs CPURegs:$dst), (ins addrlabel:$label),
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"la $dst, $label", []>;
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//===----------------------------------------------------------------------===//
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@ -414,7 +414,7 @@ def ORi : LogicI<0x0d, "ori", or>;
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def XORi : LogicI<0x0e, "xori", xor>;
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def NOR : LogicNOR<0x00, 0x27, "nor">;
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// Shifts
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// Shifts
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def SLL : LogicR_shift_imm<0x00, "sll", shl>;
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def SRL : LogicR_shift_imm<0x02, "srl", srl>;
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def SRA : LogicR_shift_imm<0x03, "sra", sra>;
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@ -439,7 +439,7 @@ def SW : StoreM<0x2b, "sw", store>;
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def BEQ : CBranch<0x04, "beq", seteq>;
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def BNE : CBranch<0x05, "bne", setne>;
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let rt=1 in
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let rt=1 in
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def BGEZ : CBranchZero<0x01, "bgez", setge>;
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let rt=0 in {
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@ -472,30 +472,33 @@ def MULTu : MulDiv<0x19, "multu", IIImul>;
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def DIV : MulDiv<0x1a, "div", IIIdiv>;
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def DIVu : MulDiv<0x1b, "divu", IIIdiv>;
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// Move From Hi/Lo
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// Move From Hi/Lo
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def MFHI : MoveFromTo<0x10, "mfhi">;
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def MFLO : MoveFromTo<0x12, "mflo">;
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def MTHI : MoveFromTo<0x11, "mthi">;
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def MTLO : MoveFromTo<0x13, "mtlo">;
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// Count Leading
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def CLO : CountLeading<0x21, "clo">;
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def CLZ : CountLeading<0x20, "clz">;
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// CLO/CLZ are part of the newer MIPS32(tm) instruction
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// set and not older Mips I keep this for future use
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// though.
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//def CLO : CountLeading<0x21, "clo">;
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//def CLZ : CountLeading<0x20, "clz">;
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// No operation
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let addr=0 in
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def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
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// Ret instruction - as mips does not have "ret" a
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// Ret instruction - as mips does not have "ret" a
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// jr $ra must be generated.
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let isReturn=1, isTerminator=1, hasDelaySlot=1,
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isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in
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isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in
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{
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def RET : FR <0x00, 0x02, (outs), (ins CPURegs:$target),
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"jr $target", [(MipsRet CPURegs:$target)], IIBranch>;
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}
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// FrameIndexes are legalized when they are operands from load/store
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// FrameIndexes are legalized when they are operands from load/store
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// instructions. The same not happens for stack address copies, so an
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// add op with mem ComplexPattern is used and the stack address copy
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// can be matched. It's similar to Sparc LEA_ADDRi
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@ -506,9 +509,9 @@ def LEA_ADDiu : EffectiveAddress<"addiu $dst, ${addr:stackloc}">;
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//===----------------------------------------------------------------------===//
|
||||
|
||||
// Small immediates
|
||||
def : Pat<(i32 immSExt16:$in),
|
||||
def : Pat<(i32 immSExt16:$in),
|
||||
(ADDiu ZERO, imm:$in)>;
|
||||
def : Pat<(i32 immZExt16:$in),
|
||||
def : Pat<(i32 immZExt16:$in),
|
||||
(ORi ZERO, imm:$in)>;
|
||||
|
||||
// Arbitrary immediates
|
||||
@ -528,17 +531,17 @@ def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
|
||||
def : Pat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
|
||||
def : Pat<(MipsAdd CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
|
||||
(ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
|
||||
def : Pat<(MipsLoadAddr tglobaladdr:$in), (LA tglobaladdr:$in)>;
|
||||
def : Pat<(MipsLoadAddr tglobaladdr:$in), (LA tglobaladdr:$in)>;
|
||||
|
||||
// Mips does not have not, so we increase the operation
|
||||
// Mips does not have not, so we increase the operation
|
||||
def : Pat<(not CPURegs:$in),
|
||||
(NOR CPURegs:$in, ZERO)>;
|
||||
|
||||
// extended load and stores
|
||||
// extended load and stores
|
||||
def : Pat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
|
||||
def : Pat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
|
||||
def : Pat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
|
||||
def : Pat<(truncstorei1 CPURegs:$src, addr:$addr),
|
||||
def : Pat<(truncstorei1 CPURegs:$src, addr:$addr),
|
||||
(SB CPURegs:$src, addr:$addr)>;
|
||||
|
||||
///
|
||||
@ -585,7 +588,7 @@ def : Pat<(brcond CPURegs:$cond, bb:$dst),
|
||||
(BNE CPURegs:$cond, ZERO, bb:$dst)>;
|
||||
|
||||
///
|
||||
/// setcc patterns, only matched when there
|
||||
/// setcc patterns, only matched when there
|
||||
/// is no brcond following a setcc operation
|
||||
///
|
||||
|
||||
@ -606,16 +609,15 @@ def : Pat<(setuge CPURegs:$lhs, CPURegs:$rhs),
|
||||
(XORi (SLTu CPURegs:$lhs, CPURegs:$rhs), 1)>;
|
||||
|
||||
def : Pat<(setne CPURegs:$lhs, CPURegs:$rhs),
|
||||
(OR (SLT CPURegs:$lhs, CPURegs:$rhs),
|
||||
(OR (SLT CPURegs:$lhs, CPURegs:$rhs),
|
||||
(SLT CPURegs:$rhs, CPURegs:$lhs))>;
|
||||
|
||||
def : Pat<(seteq CPURegs:$lhs, CPURegs:$rhs),
|
||||
(XORi (OR (SLT CPURegs:$lhs, CPURegs:$rhs),
|
||||
(XORi (OR (SLT CPURegs:$lhs, CPURegs:$rhs),
|
||||
(SLT CPURegs:$rhs, CPURegs:$lhs)), 1)>;
|
||||
|
||||
|
||||
// setcc reg/imm operands
|
||||
def : Pat<(setge CPURegs:$lhs, immSExt16:$rhs),
|
||||
(XORi (SLTi CPURegs:$lhs, immSExt16:$rhs), 1)>;
|
||||
def : Pat<(setuge CPURegs:$lhs, immZExt16:$rhs),
|
||||
(XORi (SLTiu CPURegs:$lhs, immZExt16:$rhs), 1)>;
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user