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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-16 11:30:51 +00:00
Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for a bunch of SSE2 integer arithmetic instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171092 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
a05f7cbbde
commit
3cdc3827ce
@ -2680,27 +2680,29 @@ multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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} // ExeDomain = SSEPackedInt
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multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
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ValueType OpVT128, ValueType OpVT256,
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OpndItins itins, bit IsCommutable = 0> {
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let Predicates = [HasAVX] in
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defm VP#NAME# : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, v2i64,
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defm VP#NAME# : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
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VR128, memopv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
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let Constraints = "$src1 = $dst" in
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defm P#NAME# : PDI_binop_rm<opc, OpcodeStr, Opcode, v2i64, VR128, memopv2i64,
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defm P#NAME# : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128, memopv2i64,
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i128mem, itins, IsCommutable>;
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let Predicates = [HasAVX2] in
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defm VP#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, v4i64,
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VR256, memopv4i64, i256mem, itins, IsCommutable,
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0>, VEX_4V, VEX_L;
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defm VP#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
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OpVT256, VR256, memopv4i64, i256mem, itins,
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IsCommutable, 0>, VEX_4V, VEX_L;
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}
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// These are ordered here for pattern ordering requirements with the fp versions
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defm AND : PDI_binop_all<0xDB, "pand", and, SSE_BIT_ITINS_P, 1>;
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defm OR : PDI_binop_all<0xEB, "por", or, SSE_BIT_ITINS_P, 1>;
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defm XOR : PDI_binop_all<0xEF, "pxor", xor, SSE_BIT_ITINS_P, 1>;
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defm ANDN : PDI_binop_all<0xDF, "pandn", X86andnp, SSE_BIT_ITINS_P, 0>;
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defm AND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
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defm OR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
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defm XOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
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defm ANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64,
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SSE_BIT_ITINS_P, 0>;
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//===----------------------------------------------------------------------===//
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// SSE 1 & 2 - Logical Instructions
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@ -3680,45 +3682,43 @@ multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
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}
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} // ExeDomain = SSEPackedInt
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defm ADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8,
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SSE_INTALU_ITINS_P, 1>;
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defm ADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16,
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SSE_INTALU_ITINS_P, 1>;
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defm ADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32,
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SSE_INTALU_ITINS_P, 1>;
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defm ADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64,
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SSE_INTALUQ_ITINS_P, 1>;
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defm MULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16,
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SSE_INTMUL_ITINS_P, 1>;
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defm SUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8,
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SSE_INTALU_ITINS_P, 0>;
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defm SUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16,
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SSE_INTALU_ITINS_P, 0>;
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defm SUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32,
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SSE_INTALU_ITINS_P, 0>;
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defm SUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64,
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SSE_INTALUQ_ITINS_P, 0>;
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defm SUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8,
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SSE_INTALU_ITINS_P, 0>;
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defm SUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16,
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SSE_INTALU_ITINS_P, 0>;
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defm MINUB : PDI_binop_all<0xDA, "pminub", X86umin, v16i8, v32i8,
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SSE_INTALU_ITINS_P, 1>;
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defm MINSW : PDI_binop_all<0xEA, "pminsw", X86smin, v8i16, v16i16,
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SSE_INTALU_ITINS_P, 1>;
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defm MAXUB : PDI_binop_all<0xDE, "pmaxub", X86umax, v16i8, v32i8,
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SSE_INTALU_ITINS_P, 1>;
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defm MAXSW : PDI_binop_all<0xEE, "vpmaxsw", X86smax, v8i16, v16i16,
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SSE_INTALU_ITINS_P, 1>;
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// 128-bit Integer Arithmetic
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let Predicates = [HasAVX] in {
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defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, VR128, memopv2i64,
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i128mem, SSE_INTALU_ITINS_P, 1, 0 /*3addr*/>,
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VEX_4V;
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defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, VR128, memopv2i64,
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i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
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defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, VR128, memopv2i64,
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i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
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defm VPADDQ : PDI_binop_rm<0xD4, "vpaddq", add, v2i64, VR128, memopv2i64,
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i128mem, SSE_INTALUQ_ITINS_P, 1, 0>, VEX_4V;
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defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, VR128, memopv2i64,
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i128mem, SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
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defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, VR128, memopv2i64,
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i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
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defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, VR128, memopv2i64,
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i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
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defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, VR128, memopv2i64,
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i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
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defm VPSUBQ : PDI_binop_rm<0xFB, "vpsubq", sub, v2i64, VR128, memopv2i64,
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i128mem, SSE_INTALUQ_ITINS_P, 0, 0>, VEX_4V;
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defm VPSUBUSB : PDI_binop_rm<0xD8, "vpsubusb", X86subus, v16i8, VR128,
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memopv2i64, i128mem, SSE_INTALU_ITINS_P, 0, 0>,
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VEX_4V;
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defm VPSUBUSW : PDI_binop_rm<0xD9, "vpsubusw", X86subus, v8i16, VR128,
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memopv2i64, i128mem, SSE_INTALU_ITINS_P, 0, 0>,
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VEX_4V;
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defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
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memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
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VEX_4V;
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defm VPMINUB : PDI_binop_rm<0xDA, "vpminub", X86umin, v16i8, VR128, memopv2i64,
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i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
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defm VPMINSW : PDI_binop_rm<0xEA, "vpminsw", X86smin, v8i16, VR128, memopv2i64,
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i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
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defm VPMAXUB : PDI_binop_rm<0xDE, "vpmaxub", X86umax, v16i8, VR128, memopv2i64,
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i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
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defm VPMAXSW : PDI_binop_rm<0xEE, "vpmaxsw", X86smax, v8i16, VR128, memopv2i64,
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i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
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// Intrinsic forms
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defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b,
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@ -3760,45 +3760,9 @@ defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw,
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}
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let Predicates = [HasAVX2] in {
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defm VPADDBY : PDI_binop_rm<0xFC, "vpaddb", add, v32i8, VR256, memopv4i64,
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i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
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defm VPADDWY : PDI_binop_rm<0xFD, "vpaddw", add, v16i16, VR256, memopv4i64,
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i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
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defm VPADDDY : PDI_binop_rm<0xFE, "vpaddd", add, v8i32, VR256, memopv4i64,
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i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
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defm VPADDQY : PDI_binop_rm<0xD4, "vpaddq", add, v4i64, VR256, memopv4i64,
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i256mem, SSE_INTALUQ_ITINS_P, 1, 0>, VEX_4V, VEX_L;
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defm VPMULLWY : PDI_binop_rm<0xD5, "vpmullw", mul, v16i16, VR256, memopv4i64,
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i256mem, SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
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defm VPSUBBY : PDI_binop_rm<0xF8, "vpsubb", sub, v32i8, VR256, memopv4i64,
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i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
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defm VPSUBWY : PDI_binop_rm<0xF9, "vpsubw", sub, v16i16,VR256, memopv4i64,
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i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
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defm VPSUBDY : PDI_binop_rm<0xFA, "vpsubd", sub, v8i32, VR256, memopv4i64,
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i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
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defm VPSUBQY : PDI_binop_rm<0xFB, "vpsubq", sub, v4i64, VR256, memopv4i64,
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i256mem, SSE_INTALUQ_ITINS_P, 0, 0>, VEX_4V, VEX_L;
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defm VPSUBUSBY : PDI_binop_rm<0xD8, "vpsubusb", X86subus, v32i8, VR256,
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memopv4i64, i256mem, SSE_INTALU_ITINS_P, 0, 0>,
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VEX_4V, VEX_L;
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defm VPSUBUSWY : PDI_binop_rm<0xD9, "vpsubusw", X86subus, v16i16, VR256,
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memopv4i64, i256mem, SSE_INTALU_ITINS_P, 0, 0>,
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VEX_4V, VEX_L;
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defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
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VR256, memopv4i64, i256mem,
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SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
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defm VPMINUBY : PDI_binop_rm<0xDA, "vpminub", X86umin, v32i8,
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VR256, memopv4i64, i256mem,
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SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
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defm VPMINSWY : PDI_binop_rm<0xEA, "vpminsw", X86smin, v16i16,
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VR256, memopv4i64, i256mem,
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SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
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defm VPMAXUBY : PDI_binop_rm<0xDE, "vpmaxub", X86umax, v32i8,
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VR256, memopv4i64, i256mem,
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SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
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defm VPMAXSWY : PDI_binop_rm<0xEE, "vpmaxsw", X86smax, v16i16,
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VR256, memopv4i64, i256mem,
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SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
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// Intrinsic forms
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defm VPSUBSBY : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_avx2_psubs_b,
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@ -3840,38 +3804,8 @@ defm VPSADBWY : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_avx2_psad_bw,
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}
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let Constraints = "$src1 = $dst" in {
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defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, VR128, memopv2i64,
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i128mem, SSE_INTALU_ITINS_P, 1>;
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defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, VR128, memopv2i64,
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i128mem, SSE_INTALU_ITINS_P, 1>;
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defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, VR128, memopv2i64,
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i128mem, SSE_INTALU_ITINS_P, 1>;
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defm PADDQ : PDI_binop_rm<0xD4, "paddq", add, v2i64, VR128, memopv2i64,
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i128mem, SSE_INTALUQ_ITINS_P, 1>;
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defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, VR128, memopv2i64,
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i128mem, SSE_INTMUL_ITINS_P, 1>;
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defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8, VR128, memopv2i64,
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i128mem, SSE_INTALU_ITINS_P>;
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defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16, VR128, memopv2i64,
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i128mem, SSE_INTALU_ITINS_P>;
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defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32, VR128, memopv2i64,
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i128mem, SSE_INTALU_ITINS_P>;
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defm PSUBQ : PDI_binop_rm<0xFB, "psubq", sub, v2i64, VR128, memopv2i64,
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i128mem, SSE_INTALUQ_ITINS_P>;
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defm PSUBUSB : PDI_binop_rm<0xD8, "psubusb", X86subus, v16i8, VR128, memopv2i64,
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i128mem, SSE_INTALU_ITINS_P>;
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defm PSUBUSW : PDI_binop_rm<0xD9, "psubusw", X86subus, v8i16, VR128, memopv2i64,
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i128mem, SSE_INTALU_ITINS_P>;
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defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
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memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
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defm PMINUB : PDI_binop_rm<0xDA, "pminub", X86umin, v16i8, VR128, memopv2i64,
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i128mem, SSE_INTALU_ITINS_P, 1>;
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defm PMINSW : PDI_binop_rm<0xEA, "pminsw", X86smin, v8i16, VR128, memopv2i64,
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i128mem, SSE_INTALU_ITINS_P, 1>;
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defm PMAXUB : PDI_binop_rm<0xDE, "pmaxub", X86umax, v16i8, VR128, memopv2i64,
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i128mem, SSE_INTALU_ITINS_P, 1>;
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defm PMAXSW : PDI_binop_rm<0xEE, "pmaxsw", X86smax, v8i16, VR128, memopv2i64,
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i128mem, SSE_INTALU_ITINS_P, 1>;
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// Intrinsic forms
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defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b,
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