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https://github.com/c64scene-ar/llvm-6502.git
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[Hexagon] Converting old patterns to new versions using classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226304 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu
parent
785ee4f5da
commit
3cec3682bb
@ -237,6 +237,251 @@ def F2_sfcmpeq : T_fcmp32<"sfcmp.eq", setoeq, 0b011>;
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def F2_sfcmpgt : T_fcmp32<"sfcmp.gt", setogt, 0b100>;
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}
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//===----------------------------------------------------------------------===//
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// Multiclass to define 'Def Pats' for ordered gt, ge, eq operations.
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//===----------------------------------------------------------------------===//
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let Predicates = [HasV5T] in
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multiclass T_fcmp_pats<PatFrag cmpOp, InstHexagon IntMI, InstHexagon DoubleMI> {
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// IntRegs
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def: Pat<(i1 (cmpOp F32:$src1, F32:$src2)),
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(IntMI F32:$src1, F32:$src2)>;
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// DoubleRegs
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def: Pat<(i1 (cmpOp F64:$src1, F64:$src2)),
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(DoubleMI F64:$src1, F64:$src2)>;
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}
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defm : T_fcmp_pats <seteq, F2_sfcmpeq, F2_dfcmpeq>;
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defm : T_fcmp_pats <setgt, F2_sfcmpgt, F2_dfcmpgt>;
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defm : T_fcmp_pats <setge, F2_sfcmpge, F2_dfcmpge>;
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//===----------------------------------------------------------------------===//
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// Multiclass to define 'Def Pats' for unordered gt, ge, eq operations.
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//===----------------------------------------------------------------------===//
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let Predicates = [HasV5T] in
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multiclass unord_Pats <PatFrag cmpOp, InstHexagon IntMI, InstHexagon DoubleMI> {
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// IntRegs
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def: Pat<(i1 (cmpOp F32:$src1, F32:$src2)),
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(C2_or (F2_sfcmpuo F32:$src1, F32:$src2),
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(IntMI F32:$src1, F32:$src2))>;
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// DoubleRegs
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def: Pat<(i1 (cmpOp F64:$src1, F64:$src2)),
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(C2_or (F2_dfcmpuo F64:$src1, F64:$src2),
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(DoubleMI F64:$src1, F64:$src2))>;
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}
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defm : unord_Pats <setuge, F2_sfcmpge, F2_dfcmpge>;
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defm : unord_Pats <setugt, F2_sfcmpgt, F2_dfcmpgt>;
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defm : unord_Pats <setueq, F2_sfcmpeq, F2_dfcmpeq>;
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//===----------------------------------------------------------------------===//
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// Multiclass to define 'Def Pats' for the following dags:
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// seteq(setoeq(op1, op2), 0) -> not(setoeq(op1, op2))
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// seteq(setoeq(op1, op2), 1) -> setoeq(op1, op2)
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// setne(setoeq(op1, op2), 0) -> setoeq(op1, op2)
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// setne(setoeq(op1, op2), 1) -> not(setoeq(op1, op2))
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//===----------------------------------------------------------------------===//
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let Predicates = [HasV5T] in
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multiclass eq_ordgePats <PatFrag cmpOp, InstHexagon IntMI,
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InstHexagon DoubleMI> {
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// IntRegs
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def: Pat<(i1 (seteq (i1 (cmpOp F32:$src1, F32:$src2)), 0)),
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(C2_not (IntMI F32:$src1, F32:$src2))>;
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def: Pat<(i1 (seteq (i1 (cmpOp F32:$src1, F32:$src2)), 1)),
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(IntMI F32:$src1, F32:$src2)>;
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def: Pat<(i1 (setne (i1 (cmpOp F32:$src1, F32:$src2)), 0)),
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(IntMI F32:$src1, F32:$src2)>;
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def: Pat<(i1 (setne (i1 (cmpOp F32:$src1, F32:$src2)), 1)),
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(C2_not (IntMI F32:$src1, F32:$src2))>;
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// DoubleRegs
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def : Pat<(i1 (seteq (i1 (cmpOp F64:$src1, F64:$src2)), 0)),
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(C2_not (DoubleMI F64:$src1, F64:$src2))>;
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def : Pat<(i1 (seteq (i1 (cmpOp F64:$src1, F64:$src2)), 1)),
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(DoubleMI F64:$src1, F64:$src2)>;
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def : Pat<(i1 (setne (i1 (cmpOp F64:$src1, F64:$src2)), 0)),
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(DoubleMI F64:$src1, F64:$src2)>;
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def : Pat<(i1 (setne (i1 (cmpOp F64:$src1, F64:$src2)), 1)),
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(C2_not (DoubleMI F64:$src1, F64:$src2))>;
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}
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defm : eq_ordgePats<setoeq, F2_sfcmpeq, F2_dfcmpeq>;
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defm : eq_ordgePats<setoge, F2_sfcmpge, F2_dfcmpge>;
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defm : eq_ordgePats<setogt, F2_sfcmpgt, F2_dfcmpgt>;
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//===----------------------------------------------------------------------===//
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// Multiclass to define 'Def Pats' for the following dags:
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// seteq(setolt(op1, op2), 0) -> not(setogt(op2, op1))
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// seteq(setolt(op1, op2), 1) -> setogt(op2, op1)
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// setne(setolt(op1, op2), 0) -> setogt(op2, op1)
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// setne(setolt(op1, op2), 1) -> not(setogt(op2, op1))
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//===----------------------------------------------------------------------===//
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let Predicates = [HasV5T] in
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multiclass eq_ordltPats <PatFrag cmpOp, InstHexagon IntMI,
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InstHexagon DoubleMI> {
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// IntRegs
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def: Pat<(i1 (seteq (i1 (cmpOp F32:$src1, F32:$src2)), 0)),
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(C2_not (IntMI F32:$src2, F32:$src1))>;
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def: Pat<(i1 (seteq (i1 (cmpOp F32:$src1, F32:$src2)), 1)),
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(IntMI F32:$src2, F32:$src1)>;
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def: Pat<(i1 (setne (i1 (cmpOp F32:$src1, F32:$src2)), 0)),
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(IntMI F32:$src2, F32:$src1)>;
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def: Pat<(i1 (setne (i1 (cmpOp F32:$src1, F32:$src2)), 1)),
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(C2_not (IntMI F32:$src2, F32:$src1))>;
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// DoubleRegs
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def: Pat<(i1 (seteq (i1 (cmpOp F64:$src1, F64:$src2)), 0)),
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(C2_not (DoubleMI F64:$src2, F64:$src1))>;
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def: Pat<(i1 (seteq (i1 (cmpOp F64:$src1, F64:$src2)), 1)),
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(DoubleMI F64:$src2, F64:$src1)>;
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def: Pat<(i1 (setne (i1 (cmpOp F64:$src1, F64:$src2)), 0)),
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(DoubleMI F64:$src2, F64:$src1)>;
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def: Pat<(i1 (setne (i1 (cmpOp F64:$src1, F64:$src2)), 0)),
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(C2_not (DoubleMI F64:$src2, F64:$src1))>;
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}
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defm : eq_ordltPats<setole, F2_sfcmpge, F2_dfcmpge>;
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defm : eq_ordltPats<setolt, F2_sfcmpgt, F2_dfcmpgt>;
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// o. seto inverse of setuo. http://llvm.org/docs/LangRef.html#i_fcmp
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let Predicates = [HasV5T] in {
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def: Pat<(i1 (seto F32:$src1, F32:$src2)),
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(C2_not (F2_sfcmpuo F32:$src2, F32:$src1))>;
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def: Pat<(i1 (seto F32:$src1, fpimm:$src2)),
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(C2_not (F2_sfcmpuo (TFRI_f fpimm:$src2), F32:$src1))>;
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def: Pat<(i1 (seto F64:$src1, F64:$src2)),
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(C2_not (F2_dfcmpuo F64:$src2, F64:$src1))>;
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def: Pat<(i1 (seto F64:$src1, fpimm:$src2)),
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(C2_not (F2_dfcmpuo (CONST64_Float_Real fpimm:$src2), F64:$src1))>;
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}
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// Ordered lt.
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let Predicates = [HasV5T] in {
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def: Pat<(i1 (setolt F32:$src1, F32:$src2)),
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(F2_sfcmpgt F32:$src2, F32:$src1)>;
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def: Pat<(i1 (setolt F32:$src1, fpimm:$src2)),
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(F2_sfcmpgt (f32 (TFRI_f fpimm:$src2)), F32:$src1)>;
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def: Pat<(i1 (setolt F64:$src1, F64:$src2)),
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(F2_dfcmpgt F64:$src2, F64:$src1)>;
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def: Pat<(i1 (setolt F64:$src1, fpimm:$src2)),
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(F2_dfcmpgt (CONST64_Float_Real fpimm:$src2), F64:$src1)>;
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}
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// Unordered lt.
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let Predicates = [HasV5T] in {
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def: Pat<(i1 (setult F32:$src1, F32:$src2)),
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(C2_or (F2_sfcmpuo F32:$src1, F32:$src2),
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(F2_sfcmpgt F32:$src2, F32:$src1))>;
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def: Pat<(i1 (setult F32:$src1, fpimm:$src2)),
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(C2_or (F2_sfcmpuo F32:$src1, (TFRI_f fpimm:$src2)),
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(F2_sfcmpgt (TFRI_f fpimm:$src2), F32:$src1))>;
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def: Pat<(i1 (setult F64:$src1, F64:$src2)),
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(C2_or (F2_dfcmpuo F64:$src1, F64:$src2),
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(F2_dfcmpgt F64:$src2, F64:$src1))>;
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def: Pat<(i1 (setult F64:$src1, fpimm:$src2)),
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(C2_or (F2_dfcmpuo F64:$src1, (CONST64_Float_Real fpimm:$src2)),
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(F2_dfcmpgt (CONST64_Float_Real fpimm:$src2), F64:$src1))>;
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}
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// Ordered le.
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let Predicates = [HasV5T] in {
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// rs <= rt -> rt >= rs.
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def: Pat<(i1 (setole F32:$src1, F32:$src2)),
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(F2_sfcmpge F32:$src2, F32:$src1)>;
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def: Pat<(i1 (setole F32:$src1, fpimm:$src2)),
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(F2_sfcmpge (TFRI_f fpimm:$src2), F32:$src1)>;
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// Rss <= Rtt -> Rtt >= Rss.
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def: Pat<(i1 (setole F64:$src1, F64:$src2)),
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(F2_dfcmpge F64:$src2, F64:$src1)>;
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def: Pat<(i1 (setole F64:$src1, fpimm:$src2)),
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(F2_dfcmpge (CONST64_Float_Real fpimm:$src2), F64:$src1)>;
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}
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// Unordered le.
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let Predicates = [HasV5T] in {
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// rs <= rt -> rt >= rs.
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def: Pat<(i1 (setule F32:$src1, F32:$src2)),
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(C2_or (F2_sfcmpuo F32:$src1, F32:$src2),
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(F2_sfcmpge F32:$src2, F32:$src1))>;
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def: Pat<(i1 (setule F32:$src1, fpimm:$src2)),
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(C2_or (F2_sfcmpuo F32:$src1, (TFRI_f fpimm:$src2)),
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(F2_sfcmpge (TFRI_f fpimm:$src2), F32:$src1))>;
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def: Pat<(i1 (setule F64:$src1, F64:$src2)),
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(C2_or (F2_dfcmpuo F64:$src1, F64:$src2),
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(F2_dfcmpge F64:$src2, F64:$src1))>;
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def: Pat<(i1 (setule F64:$src1, fpimm:$src2)),
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(C2_or (F2_dfcmpuo F64:$src1, (CONST64_Float_Real fpimm:$src2)),
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(F2_dfcmpge (CONST64_Float_Real fpimm:$src2), F64:$src1))>;
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}
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// Ordered ne.
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let Predicates = [HasV5T] in {
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def: Pat<(i1 (setone F32:$src1, F32:$src2)),
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(C2_not (F2_sfcmpeq F32:$src1, F32:$src2))>;
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def: Pat<(i1 (setone F64:$src1, F64:$src2)),
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(C2_not (F2_dfcmpeq F64:$src1, F64:$src2))>;
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def: Pat<(i1 (setone F32:$src1, fpimm:$src2)),
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(C2_not (F2_sfcmpeq F32:$src1, (TFRI_f fpimm:$src2)))>;
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def: Pat<(i1 (setone F64:$src1, fpimm:$src2)),
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(C2_not (F2_dfcmpeq F64:$src1, (CONST64_Float_Real fpimm:$src2)))>;
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}
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// Unordered ne.
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let Predicates = [HasV5T] in {
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def: Pat<(i1 (setune F32:$src1, F32:$src2)),
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(C2_or (F2_sfcmpuo F32:$src1, F32:$src2),
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(C2_not (F2_sfcmpeq F32:$src1, F32:$src2)))>;
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def: Pat<(i1 (setune F64:$src1, F64:$src2)),
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(C2_or (F2_dfcmpuo F64:$src1, F64:$src2),
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(C2_not (F2_dfcmpeq F64:$src1, F64:$src2)))>;
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def: Pat<(i1 (setune F32:$src1, fpimm:$src2)),
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(C2_or (F2_sfcmpuo F32:$src1, (TFRI_f fpimm:$src2)),
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(C2_not (F2_sfcmpeq F32:$src1, (TFRI_f fpimm:$src2))))>;
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def: Pat<(i1 (setune F64:$src1, fpimm:$src2)),
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(C2_or (F2_dfcmpuo F64:$src1, (CONST64_Float_Real fpimm:$src2)),
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(C2_not (F2_dfcmpeq F64:$src1,
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(CONST64_Float_Real fpimm:$src2))))>;
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}
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// Besides set[o|u][comparions], we also need set[comparisons].
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let Predicates = [HasV5T] in {
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// lt.
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def: Pat<(i1 (setlt F32:$src1, F32:$src2)),
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(F2_sfcmpgt F32:$src2, F32:$src1)>;
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def: Pat<(i1 (setlt F32:$src1, fpimm:$src2)),
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(F2_sfcmpgt (TFRI_f fpimm:$src2), F32:$src1)>;
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def: Pat<(i1 (setlt F64:$src1, F64:$src2)),
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(F2_dfcmpgt F64:$src2, F64:$src1)>;
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def: Pat<(i1 (setlt F64:$src1, fpimm:$src2)),
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(F2_dfcmpgt (CONST64_Float_Real fpimm:$src2), F64:$src1)>;
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// le.
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// rs <= rt -> rt >= rs.
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def: Pat<(i1 (setle F32:$src1, F32:$src2)),
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(F2_sfcmpge F32:$src2, F32:$src1)>;
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def: Pat<(i1 (setle F32:$src1, fpimm:$src2)),
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(F2_sfcmpge (TFRI_f fpimm:$src2), F32:$src1)>;
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// Rss <= Rtt -> Rtt >= Rss.
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def: Pat<(i1 (setle F64:$src1, F64:$src2)),
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(F2_dfcmpge F64:$src2, F64:$src1)>;
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def: Pat<(i1 (setle F64:$src1, fpimm:$src2)),
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(F2_dfcmpge (CONST64_Float_Real fpimm:$src2), F64:$src1)>;
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// ne.
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def: Pat<(i1 (setne F32:$src1, F32:$src2)),
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(C2_not (F2_sfcmpeq F32:$src1, F32:$src2))>;
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def: Pat<(i1 (setne F64:$src1, F64:$src2)),
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(C2_not (F2_dfcmpeq F64:$src1, F64:$src2))>;
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def: Pat<(i1 (setne F32:$src1, fpimm:$src2)),
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(C2_not (F2_sfcmpeq F32:$src1, (TFRI_f fpimm:$src2)))>;
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def: Pat<(i1 (setne F64:$src1, fpimm:$src2)),
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(C2_not (F2_dfcmpeq F64:$src1, (CONST64_Float_Real fpimm:$src2)))>;
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}
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// F2 convert template classes:
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let isFP = 1 in
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class F2_RDD_RSS_CONVERT<string mnemonic, bits<3> MinOp,
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@ -397,6 +642,14 @@ def F2_sffixupr: SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs),
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let Inst{4-0} = Rd;
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}
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// Bitcast is different than [fp|sint|uint]_to_[sint|uint|fp].
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let Predicates = [HasV5T] in {
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def: Pat <(i32 (bitconvert F32:$src)), (I32:$src)>;
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def: Pat <(f32 (bitconvert I32:$src)), (F32:$src)>;
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def: Pat <(i64 (bitconvert F64:$src)), (I64:$src)>;
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def: Pat <(f64 (bitconvert I64:$src)), (F64:$src)>;
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}
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// F2_sffma: Floating-point fused multiply add.
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let isFP = 1, hasNewValue = 1 in
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class T_sfmpy_acc <bit isSub, bit isLib>
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@ -514,170 +767,6 @@ def F2_dfimm_p : T_fimm <"dfmake", DoubleRegs, 0b1001, 0>;
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def F2_dfimm_n : T_fimm <"dfmake", DoubleRegs, 0b1001, 1>;
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}
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// olt.
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def : Pat <(i1 (setolt (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
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(i1 (F2_sfcmpgt IntRegs:$src2, IntRegs:$src1))>,
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Requires<[HasV5T]>;
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def : Pat <(i1 (setolt (f32 IntRegs:$src1), (fpimm:$src2))),
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(i1 (F2_sfcmpgt (f32 (TFRI_f fpimm:$src2)), (f32 IntRegs:$src1)))>,
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Requires<[HasV5T]>;
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def : Pat <(i1 (setolt (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
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(i1 (F2_dfcmpgt DoubleRegs:$src2, DoubleRegs:$src1))>,
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Requires<[HasV5T]>;
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def : Pat <(i1 (setolt (f64 DoubleRegs:$src1), (fpimm:$src2))),
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(i1 (F2_dfcmpgt (f64 (CONST64_Float_Real fpimm:$src2)),
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(f64 DoubleRegs:$src1)))>,
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Requires<[HasV5T]>;
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// gt.
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def : Pat <(i1 (setugt (f64 DoubleRegs:$src1), (fpimm:$src2))),
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(i1 (F2_dfcmpgt (f64 DoubleRegs:$src1),
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(f64 (CONST64_Float_Real fpimm:$src2))))>,
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Requires<[HasV5T]>;
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def : Pat <(i1 (setugt (f32 IntRegs:$src1), (fpimm:$src2))),
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(i1 (F2_sfcmpgt (f32 IntRegs:$src1), (f32 (TFRI_f fpimm:$src2))))>,
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Requires<[HasV5T]>;
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// ult.
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def : Pat <(i1 (setult (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
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(i1 (F2_sfcmpgt IntRegs:$src2, IntRegs:$src1))>,
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Requires<[HasV5T]>;
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def : Pat <(i1 (setult (f32 IntRegs:$src1), (fpimm:$src2))),
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(i1 (F2_sfcmpgt (f32 (TFRI_f fpimm:$src2)), (f32 IntRegs:$src1)))>,
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Requires<[HasV5T]>;
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def : Pat <(i1 (setult (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
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(i1 (F2_dfcmpgt DoubleRegs:$src2, DoubleRegs:$src1))>,
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Requires<[HasV5T]>;
|
||||
|
||||
def : Pat <(i1 (setult (f64 DoubleRegs:$src1), (fpimm:$src2))),
|
||||
(i1 (F2_dfcmpgt (f64 (CONST64_Float_Real fpimm:$src2)),
|
||||
(f64 DoubleRegs:$src1)))>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
// le.
|
||||
// rs <= rt -> rt >= rs.
|
||||
def : Pat<(i1 (setole (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
|
||||
(i1 (F2_sfcmpge IntRegs:$src2, IntRegs:$src1))>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
def : Pat<(i1 (setole (f32 IntRegs:$src1), (fpimm:$src2))),
|
||||
(i1 (F2_sfcmpge (f32 (TFRI_f fpimm:$src2)), IntRegs:$src1))>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
|
||||
// Rss <= Rtt -> Rtt >= Rss.
|
||||
def : Pat<(i1 (setole (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
|
||||
(i1 (F2_dfcmpge DoubleRegs:$src2, DoubleRegs:$src1))>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
def : Pat<(i1 (setole (f64 DoubleRegs:$src1), (fpimm:$src2))),
|
||||
(i1 (F2_dfcmpge (f64 (CONST64_Float_Real fpimm:$src2)),
|
||||
DoubleRegs:$src1))>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
// rs <= rt -> rt >= rs.
|
||||
def : Pat<(i1 (setule (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
|
||||
(i1 (F2_sfcmpge IntRegs:$src2, IntRegs:$src1))>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
def : Pat<(i1 (setule (f32 IntRegs:$src1), (fpimm:$src2))),
|
||||
(i1 (F2_sfcmpge (f32 (TFRI_f fpimm:$src2)), IntRegs:$src1))>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
// Rss <= Rtt -> Rtt >= Rss.
|
||||
def : Pat<(i1 (setule (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
|
||||
(i1 (F2_dfcmpge DoubleRegs:$src2, DoubleRegs:$src1))>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
def : Pat<(i1 (setule (f64 DoubleRegs:$src1), (fpimm:$src2))),
|
||||
(i1 (F2_dfcmpge (f64 (CONST64_Float_Real fpimm:$src2)),
|
||||
DoubleRegs:$src1))>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
// ne.
|
||||
def : Pat<(i1 (setone (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
|
||||
(i1 (C2_not (F2_sfcmpeq IntRegs:$src1, IntRegs:$src2)))>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
def : Pat<(i1 (setone (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
|
||||
(i1 (C2_not (F2_dfcmpeq DoubleRegs:$src1, DoubleRegs:$src2)))>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
def : Pat<(i1 (setune (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
|
||||
(i1 (C2_not (F2_sfcmpeq IntRegs:$src1, IntRegs:$src2)))>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
def : Pat<(i1 (setune (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
|
||||
(i1 (C2_not (F2_dfcmpeq DoubleRegs:$src1, DoubleRegs:$src2)))>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
def : Pat<(i1 (setone (f32 IntRegs:$src1), (fpimm:$src2))),
|
||||
(i1 (C2_not (F2_sfcmpeq IntRegs:$src1, (f32 (TFRI_f fpimm:$src2)))))>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
def : Pat<(i1 (setone (f64 DoubleRegs:$src1), (fpimm:$src2))),
|
||||
(i1 (C2_not (F2_dfcmpeq DoubleRegs:$src1,
|
||||
(f64 (CONST64_Float_Real fpimm:$src2)))))>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
def : Pat<(i1 (setune (f32 IntRegs:$src1), (fpimm:$src2))),
|
||||
(i1 (C2_not (F2_sfcmpeq IntRegs:$src1, (f32 (TFRI_f fpimm:$src2)))))>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
def : Pat<(i1 (setune (f64 DoubleRegs:$src1), (fpimm:$src2))),
|
||||
(i1 (C2_not (F2_dfcmpeq DoubleRegs:$src1,
|
||||
(f64 (CONST64_Float_Real fpimm:$src2)))))>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
// Bitcast is different than [fp|sint|uint]_to_[sint|uint|fp].
|
||||
def : Pat <(i32 (bitconvert (f32 IntRegs:$src))),
|
||||
(i32 (A2_tfr IntRegs:$src))>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
def : Pat <(f32 (bitconvert (i32 IntRegs:$src))),
|
||||
(f32 (A2_tfr IntRegs:$src))>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
def : Pat <(i64 (bitconvert (f64 DoubleRegs:$src))),
|
||||
(i64 (A2_tfrp DoubleRegs:$src))>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
def : Pat <(f64 (bitconvert (i64 DoubleRegs:$src))),
|
||||
(f64 (A2_tfrp DoubleRegs:$src))>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
def : Pat <(select (i1 (setult (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
|
||||
(f32 IntRegs:$src3),
|
||||
(f32 IntRegs:$src4)),
|
||||
(C2_mux (F2_sfcmpgt IntRegs:$src2, IntRegs:$src1), IntRegs:$src4,
|
||||
IntRegs:$src3)>, Requires<[HasV5T]>;
|
||||
|
||||
def : Pat <(select (i1 (setult (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
|
||||
(f64 DoubleRegs:$src3),
|
||||
(f64 DoubleRegs:$src4)),
|
||||
(C2_vmux (F2_dfcmpgt DoubleRegs:$src2, DoubleRegs:$src1),
|
||||
DoubleRegs:$src4, DoubleRegs:$src3)>, Requires<[HasV5T]>;
|
||||
|
||||
// Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
|
||||
// => r0 = TFR_condset_ri(p0, r1, #i)
|
||||
def : Pat <(select (not PredRegs:$src1), fpimm:$src2, IntRegs:$src3),
|
||||
(MUX_ri_f PredRegs:$src1, IntRegs:$src3, fpimm:$src2)>;
|
||||
|
||||
// Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
|
||||
// => r0 = TFR_condset_ir(p0, #i, r1)
|
||||
def : Pat <(select (not PredRegs:$src1), IntRegs:$src2, fpimm:$src3),
|
||||
(MUX_ir_f PredRegs:$src1, fpimm:$src3, IntRegs:$src2)>;
|
||||
|
||||
def : Pat <(i32 (fp_to_sint (f64 DoubleRegs:$src1))),
|
||||
(i32 (EXTRACT_SUBREG (i64 (F2_conv_df2d_chop (f64 DoubleRegs:$src1))), subreg_loreg))>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
def : Pat <(fabs (f32 IntRegs:$src1)),
|
||||
(S2_clrbit_i (f32 IntRegs:$src1), 31)>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user