mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
Adds Intel Atom scheduling latencies to X86InstrSystem.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156194 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Preston Gurd
parent
39af9449a2
commit
3d142e58ef
@ -14,7 +14,8 @@
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//===----------------------------------------------------------------------===//
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let Defs = [RAX, RDX] in
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def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>, TB;
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def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)], IIC_RDTSC>,
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TB;
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let Defs = [RAX, RCX, RDX] in
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def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
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@ -26,14 +27,14 @@ let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
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def UD2B : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
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}
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def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
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def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
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def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", [], IIC_HLT>;
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def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", [], IIC_RSM>, TB;
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// Interrupt and SysCall Instructions.
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let Uses = [EFLAGS] in
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def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
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def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
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[(int_x86_int (i8 3))]>;
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[(int_x86_int (i8 3))], IIC_INT3>;
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// The long form of "int $3" turns into int3 as a size optimization.
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// FIXME: This doesn't work because InstAlias can't match immediate constants.
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@ -41,23 +42,25 @@ def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
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def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap",
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[(int_x86_int imm:$trap)]>;
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[(int_x86_int imm:$trap)], IIC_INT>;
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def SYSCALL : I<0x05, RawFrm, (outs), (ins), "syscall", []>, TB;
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def SYSRET : I<0x07, RawFrm, (outs), (ins), "sysret{l}", []>, TB;
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def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysret{q}", []>, TB,
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def SYSCALL : I<0x05, RawFrm, (outs), (ins), "syscall", [], IIC_SYSCALL>, TB;
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def SYSRET : I<0x07, RawFrm, (outs), (ins), "sysret{l}", [], IIC_SYSCALL>, TB;
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def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysret{q}", [], IIC_SYSCALL>, TB,
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Requires<[In64BitMode]>;
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def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", []>, TB;
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def SYSEXIT : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", []>, TB;
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def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", [],
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IIC_SYS_ENTER_EXIT>, TB;
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def SYSEXIT : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", [],
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IIC_SYS_ENTER_EXIT>, TB;
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def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexit{q}", []>, TB,
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Requires<[In64BitMode]>;
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def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", []>, OpSize;
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def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l|d}", []>;
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def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iretq", []>,
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def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", [], IIC_IRET>, OpSize;
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def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l|d}", [], IIC_IRET>;
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def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iretq", [], IIC_IRET>,
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Requires<[In64BitMode]>;
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@ -66,73 +69,73 @@ def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iretq", []>,
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//
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let Defs = [AL], Uses = [DX] in
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def IN8rr : I<0xEC, RawFrm, (outs), (ins),
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"in{b}\t{%dx, %al|AL, DX}", []>;
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"in{b}\t{%dx, %al|AL, DX}", [], IIC_IN_RR>;
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let Defs = [AX], Uses = [DX] in
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def IN16rr : I<0xED, RawFrm, (outs), (ins),
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"in{w}\t{%dx, %ax|AX, DX}", []>, OpSize;
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"in{w}\t{%dx, %ax|AX, DX}", [], IIC_IN_RR>, OpSize;
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let Defs = [EAX], Uses = [DX] in
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def IN32rr : I<0xED, RawFrm, (outs), (ins),
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"in{l}\t{%dx, %eax|EAX, DX}", []>;
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"in{l}\t{%dx, %eax|EAX, DX}", [], IIC_IN_RR>;
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let Defs = [AL] in
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def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i8imm:$port),
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"in{b}\t{$port, %al|AL, $port}", []>;
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"in{b}\t{$port, %al|AL, $port}", [], IIC_IN_RI>;
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let Defs = [AX] in
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def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
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"in{w}\t{$port, %ax|AX, $port}", []>, OpSize;
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"in{w}\t{$port, %ax|AX, $port}", [], IIC_IN_RI>, OpSize;
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let Defs = [EAX] in
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def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
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"in{l}\t{$port, %eax|EAX, $port}", []>;
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"in{l}\t{$port, %eax|EAX, $port}", [], IIC_IN_RI>;
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let Uses = [DX, AL] in
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def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
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"out{b}\t{%al, %dx|DX, AL}", []>;
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"out{b}\t{%al, %dx|DX, AL}", [], IIC_OUT_RR>;
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let Uses = [DX, AX] in
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def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
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"out{w}\t{%ax, %dx|DX, AX}", []>, OpSize;
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"out{w}\t{%ax, %dx|DX, AX}", [], IIC_OUT_RR>, OpSize;
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let Uses = [DX, EAX] in
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def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
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"out{l}\t{%eax, %dx|DX, EAX}", []>;
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"out{l}\t{%eax, %dx|DX, EAX}", [], IIC_OUT_RR>;
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let Uses = [AL] in
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def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i8imm:$port),
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"out{b}\t{%al, $port|$port, AL}", []>;
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"out{b}\t{%al, $port|$port, AL}", [], IIC_OUT_IR>;
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let Uses = [AX] in
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def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
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"out{w}\t{%ax, $port|$port, AX}", []>, OpSize;
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"out{w}\t{%ax, $port|$port, AX}", [], IIC_OUT_IR>, OpSize;
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let Uses = [EAX] in
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def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
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"out{l}\t{%eax, $port|$port, EAX}", []>;
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"out{l}\t{%eax, $port|$port, EAX}", [], IIC_OUT_IR>;
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def IN8 : I<0x6C, RawFrm, (outs), (ins), "ins{b}", []>;
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def IN16 : I<0x6D, RawFrm, (outs), (ins), "ins{w}", []>, OpSize;
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def IN32 : I<0x6D, RawFrm, (outs), (ins), "ins{l}", []>;
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def IN8 : I<0x6C, RawFrm, (outs), (ins), "ins{b}", [], IIC_INS>;
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def IN16 : I<0x6D, RawFrm, (outs), (ins), "ins{w}", [], IIC_INS>, OpSize;
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def IN32 : I<0x6D, RawFrm, (outs), (ins), "ins{l}", [], IIC_INS>;
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//===----------------------------------------------------------------------===//
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// Moves to and from debug registers
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def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
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"mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
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"mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB;
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def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
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"mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
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"mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB;
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def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
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"mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
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"mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB;
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def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
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"mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
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"mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB;
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//===----------------------------------------------------------------------===//
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// Moves to and from control registers
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def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
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"mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
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"mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB;
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def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
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"mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
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"mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB;
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def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
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"mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
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"mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB;
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def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
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"mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
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"mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB;
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//===----------------------------------------------------------------------===//
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// Segment override instruction prefixes
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@ -150,254 +153,265 @@ def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
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//
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def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
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"mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
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"mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize;
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def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
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"mov{l}\t{$src, $dst|$dst, $src}", []>;
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"mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>;
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def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
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"mov{q}\t{$src, $dst|$dst, $src}", []>;
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"mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>;
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def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
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"mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
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"mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize;
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def MOV32ms : I<0x8C, MRMDestMem, (outs i32mem:$dst), (ins SEGMENT_REG:$src),
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"mov{l}\t{$src, $dst|$dst, $src}", []>;
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"mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>;
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def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),
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"mov{q}\t{$src, $dst|$dst, $src}", []>;
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"mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>;
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def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
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"mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
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"mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize;
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def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
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"mov{l}\t{$src, $dst|$dst, $src}", []>;
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"mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>;
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def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
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"mov{q}\t{$src, $dst|$dst, $src}", []>;
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"mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>;
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def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
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"mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
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"mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize;
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def MOV32sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i32mem:$src),
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"mov{l}\t{$src, $dst|$dst, $src}", []>;
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"mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>;
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def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
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"mov{q}\t{$src, $dst|$dst, $src}", []>;
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"mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>;
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//===----------------------------------------------------------------------===//
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// Segmentation support instructions.
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def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", []>, TB;
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def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", [], IIC_SWAPGS>, TB;
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def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
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"lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
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"lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB, OpSize;
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def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
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"lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
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"lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB, OpSize;
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// i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
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def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
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"lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
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"lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB;
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def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
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"lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
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"lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB;
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// i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
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def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
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"lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
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"lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB;
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def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
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"lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
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"lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB;
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def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
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"lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
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"lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB, OpSize;
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def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
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"lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
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"lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB, OpSize;
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def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
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"lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
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"lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB;
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def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
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"lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
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"lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB;
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def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
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"lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
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"lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB;
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def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
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"lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
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"lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB;
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def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
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def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr",
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[], IIC_INVLPG>, TB;
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def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
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"str{w}\t$dst", []>, TB, OpSize;
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"str{w}\t$dst", [], IIC_STR>, TB, OpSize;
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def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
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"str{l}\t$dst", []>, TB;
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"str{l}\t$dst", [], IIC_STR>, TB;
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def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
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"str{q}\t$dst", []>, TB;
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"str{q}\t$dst", [], IIC_STR>, TB;
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def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
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"str{w}\t$dst", []>, TB;
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"str{w}\t$dst", [], IIC_STR>, TB;
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def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
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"ltr{w}\t$src", []>, TB;
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"ltr{w}\t$src", [], IIC_LTR>, TB;
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def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
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"ltr{w}\t$src", []>, TB;
|
||||
"ltr{w}\t$src", [], IIC_LTR>, TB;
|
||||
|
||||
def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins),
|
||||
"push{w}\t{%cs|CS}", []>, Requires<[In32BitMode]>, OpSize;
|
||||
"push{w}\t{%cs|CS}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>,
|
||||
OpSize;
|
||||
def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins),
|
||||
"push{l}\t{%cs|CS}", []>, Requires<[In32BitMode]>;
|
||||
"push{l}\t{%cs|CS}", [], IIC_PUSH_CS>, Requires<[In32BitMode]>;
|
||||
def PUSHSS16 : I<0x16, RawFrm, (outs), (ins),
|
||||
"push{w}\t{%ss|SS}", []>, Requires<[In32BitMode]>, OpSize;
|
||||
"push{w}\t{%ss|SS}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>,
|
||||
OpSize;
|
||||
def PUSHSS32 : I<0x16, RawFrm, (outs), (ins),
|
||||
"push{l}\t{%ss|SS}", []>, Requires<[In32BitMode]>;
|
||||
"push{l}\t{%ss|SS}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>;
|
||||
def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins),
|
||||
"push{w}\t{%ds|DS}", []>, Requires<[In32BitMode]>, OpSize;
|
||||
"push{w}\t{%ds|DS}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>,
|
||||
OpSize;
|
||||
def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins),
|
||||
"push{l}\t{%ds|DS}", []>, Requires<[In32BitMode]>;
|
||||
"push{l}\t{%ds|DS}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>;
|
||||
def PUSHES16 : I<0x06, RawFrm, (outs), (ins),
|
||||
"push{w}\t{%es|ES}", []>, Requires<[In32BitMode]>, OpSize;
|
||||
"push{w}\t{%es|ES}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>,
|
||||
OpSize;
|
||||
def PUSHES32 : I<0x06, RawFrm, (outs), (ins),
|
||||
"push{l}\t{%es|ES}", []>, Requires<[In32BitMode]>;
|
||||
"push{l}\t{%es|ES}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>;
|
||||
|
||||
def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
|
||||
"push{w}\t{%fs|FS}", []>, OpSize, TB;
|
||||
"push{w}\t{%fs|FS}", [], IIC_PUSH_SR>, OpSize, TB;
|
||||
def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
|
||||
"push{l}\t{%fs|FS}", []>, TB, Requires<[In32BitMode]>;
|
||||
"push{l}\t{%fs|FS}", [], IIC_PUSH_SR>, TB, Requires<[In32BitMode]>;
|
||||
def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
|
||||
"push{w}\t{%gs|GS}", []>, OpSize, TB;
|
||||
"push{w}\t{%gs|GS}", [], IIC_PUSH_SR>, OpSize, TB;
|
||||
def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
|
||||
"push{l}\t{%gs|GS}", []>, TB, Requires<[In32BitMode]>;
|
||||
"push{l}\t{%gs|GS}", [], IIC_PUSH_SR>, TB, Requires<[In32BitMode]>;
|
||||
|
||||
def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
|
||||
"push{q}\t{%fs|FS}", []>, TB;
|
||||
"push{q}\t{%fs|FS}", [], IIC_PUSH_SR>, TB;
|
||||
def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
|
||||
"push{q}\t{%gs|GS}", []>, TB;
|
||||
"push{q}\t{%gs|GS}", [], IIC_PUSH_SR>, TB;
|
||||
|
||||
// No "pop cs" instruction.
|
||||
def POPSS16 : I<0x17, RawFrm, (outs), (ins),
|
||||
"pop{w}\t{%ss|SS}", []>, OpSize, Requires<[In32BitMode]>;
|
||||
"pop{w}\t{%ss|SS}", [], IIC_POP_SR_SS>,
|
||||
OpSize, Requires<[In32BitMode]>;
|
||||
def POPSS32 : I<0x17, RawFrm, (outs), (ins),
|
||||
"pop{l}\t{%ss|SS}", []> , Requires<[In32BitMode]>;
|
||||
"pop{l}\t{%ss|SS}", [], IIC_POP_SR_SS>,
|
||||
Requires<[In32BitMode]>;
|
||||
|
||||
def POPDS16 : I<0x1F, RawFrm, (outs), (ins),
|
||||
"pop{w}\t{%ds|DS}", []>, OpSize, Requires<[In32BitMode]>;
|
||||
"pop{w}\t{%ds|DS}", [], IIC_POP_SR>,
|
||||
OpSize, Requires<[In32BitMode]>;
|
||||
def POPDS32 : I<0x1F, RawFrm, (outs), (ins),
|
||||
"pop{l}\t{%ds|DS}", []> , Requires<[In32BitMode]>;
|
||||
"pop{l}\t{%ds|DS}", [], IIC_POP_SR>,
|
||||
Requires<[In32BitMode]>;
|
||||
|
||||
def POPES16 : I<0x07, RawFrm, (outs), (ins),
|
||||
"pop{w}\t{%es|ES}", []>, OpSize, Requires<[In32BitMode]>;
|
||||
"pop{w}\t{%es|ES}", [], IIC_POP_SR>,
|
||||
OpSize, Requires<[In32BitMode]>;
|
||||
def POPES32 : I<0x07, RawFrm, (outs), (ins),
|
||||
"pop{l}\t{%es|ES}", []> , Requires<[In32BitMode]>;
|
||||
"pop{l}\t{%es|ES}", [], IIC_POP_SR>,
|
||||
Requires<[In32BitMode]>;
|
||||
|
||||
def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
|
||||
"pop{w}\t{%fs|FS}", []>, OpSize, TB;
|
||||
"pop{w}\t{%fs|FS}", [], IIC_POP_SR>, OpSize, TB;
|
||||
def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
|
||||
"pop{l}\t{%fs|FS}", []>, TB , Requires<[In32BitMode]>;
|
||||
"pop{l}\t{%fs|FS}", [], IIC_POP_SR>, TB, Requires<[In32BitMode]>;
|
||||
def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
|
||||
"pop{q}\t{%fs|FS}", []>, TB;
|
||||
"pop{q}\t{%fs|FS}", [], IIC_POP_SR>, TB;
|
||||
|
||||
def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
|
||||
"pop{w}\t{%gs|GS}", []>, OpSize, TB;
|
||||
"pop{w}\t{%gs|GS}", [], IIC_POP_SR>, OpSize, TB;
|
||||
def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
|
||||
"pop{l}\t{%gs|GS}", []>, TB , Requires<[In32BitMode]>;
|
||||
"pop{l}\t{%gs|GS}", [], IIC_POP_SR>, TB, Requires<[In32BitMode]>;
|
||||
def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
|
||||
"pop{q}\t{%gs|GS}", []>, TB;
|
||||
"pop{q}\t{%gs|GS}", [], IIC_POP_SR>, TB;
|
||||
|
||||
|
||||
def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
|
||||
"lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
|
||||
"lds{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize;
|
||||
def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
|
||||
"lds{l}\t{$src, $dst|$dst, $src}", []>;
|
||||
"lds{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>;
|
||||
|
||||
def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
|
||||
"lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
|
||||
"lss{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize;
|
||||
def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
|
||||
"lss{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
||||
"lss{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
|
||||
def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
|
||||
"lss{q}\t{$src, $dst|$dst, $src}", []>, TB;
|
||||
"lss{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
|
||||
|
||||
def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
|
||||
"les{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
|
||||
"les{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize;
|
||||
def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
|
||||
"les{l}\t{$src, $dst|$dst, $src}", []>;
|
||||
"les{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>;
|
||||
|
||||
def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
|
||||
"lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
|
||||
"lfs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize;
|
||||
def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
|
||||
"lfs{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
||||
"lfs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
|
||||
def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
|
||||
"lfs{q}\t{$src, $dst|$dst, $src}", []>, TB;
|
||||
"lfs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
|
||||
|
||||
def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
|
||||
"lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
|
||||
"lgs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize;
|
||||
def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
|
||||
"lgs{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
||||
"lgs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
|
||||
|
||||
def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
|
||||
"lgs{q}\t{$src, $dst|$dst, $src}", []>, TB;
|
||||
"lgs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
|
||||
|
||||
|
||||
def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
|
||||
"verr\t$seg", []>, TB;
|
||||
"verr\t$seg", [], IIC_VERR>, TB;
|
||||
def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
|
||||
"verr\t$seg", []>, TB;
|
||||
"verr\t$seg", [], IIC_VERR>, TB;
|
||||
def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
|
||||
"verw\t$seg", []>, TB;
|
||||
"verw\t$seg", [], IIC_VERW_MEM>, TB;
|
||||
def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
|
||||
"verw\t$seg", []>, TB;
|
||||
"verw\t$seg", [], IIC_VERW_REG>, TB;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Descriptor-table support instructions
|
||||
|
||||
def SGDT16m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
|
||||
"sgdtw\t$dst", []>, TB, OpSize, Requires<[In32BitMode]>;
|
||||
"sgdtw\t$dst", [], IIC_SGDT>, TB, OpSize, Requires<[In32BitMode]>;
|
||||
def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
|
||||
"sgdt\t$dst", []>, TB;
|
||||
"sgdt\t$dst", [], IIC_SGDT>, TB;
|
||||
def SIDT16m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
|
||||
"sidtw\t$dst", []>, TB, OpSize, Requires<[In32BitMode]>;
|
||||
"sidtw\t$dst", [], IIC_SIDT>, TB, OpSize, Requires<[In32BitMode]>;
|
||||
def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
|
||||
"sidt\t$dst", []>, TB;
|
||||
def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
|
||||
"sldt{w}\t$dst", []>, TB, OpSize;
|
||||
"sldt{w}\t$dst", [], IIC_SLDT>, TB, OpSize;
|
||||
def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
|
||||
"sldt{w}\t$dst", []>, TB;
|
||||
"sldt{w}\t$dst", [], IIC_SLDT>, TB;
|
||||
def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
|
||||
"sldt{l}\t$dst", []>, TB;
|
||||
"sldt{l}\t$dst", [], IIC_SLDT>, TB;
|
||||
|
||||
// LLDT is not interpreted specially in 64-bit mode because there is no sign
|
||||
// extension.
|
||||
def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
|
||||
"sldt{q}\t$dst", []>, TB;
|
||||
"sldt{q}\t$dst", [], IIC_SLDT>, TB;
|
||||
def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),
|
||||
"sldt{q}\t$dst", []>, TB;
|
||||
"sldt{q}\t$dst", [], IIC_SLDT>, TB;
|
||||
|
||||
def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
|
||||
"lgdtw\t$src", []>, TB, OpSize, Requires<[In32BitMode]>;
|
||||
"lgdtw\t$src", [], IIC_LGDT>, TB, OpSize, Requires<[In32BitMode]>;
|
||||
def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
|
||||
"lgdt\t$src", []>, TB;
|
||||
"lgdt\t$src", [], IIC_LGDT>, TB;
|
||||
def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
|
||||
"lidtw\t$src", []>, TB, OpSize, Requires<[In32BitMode]>;
|
||||
"lidtw\t$src", [], IIC_LIDT>, TB, OpSize, Requires<[In32BitMode]>;
|
||||
def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
|
||||
"lidt\t$src", []>, TB;
|
||||
"lidt\t$src", [], IIC_LIDT>, TB;
|
||||
def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
|
||||
"lldt{w}\t$src", []>, TB;
|
||||
"lldt{w}\t$src", [], IIC_LLDT_REG>, TB;
|
||||
def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
|
||||
"lldt{w}\t$src", []>, TB;
|
||||
"lldt{w}\t$src", [], IIC_LLDT_MEM>, TB;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Specialized register support
|
||||
def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
|
||||
def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
|
||||
def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
|
||||
def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", [], IIC_WRMSR>, TB;
|
||||
def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", [], IIC_RDMSR>, TB;
|
||||
def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", [], IIC_RDPMC>, TB;
|
||||
|
||||
def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
|
||||
"smsw{w}\t$dst", []>, OpSize, TB;
|
||||
"smsw{w}\t$dst", [], IIC_SMSW>, OpSize, TB;
|
||||
def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
|
||||
"smsw{l}\t$dst", []>, TB;
|
||||
"smsw{l}\t$dst", [], IIC_SMSW>, TB;
|
||||
// no m form encodable; use SMSW16m
|
||||
def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
|
||||
"smsw{q}\t$dst", []>, TB;
|
||||
"smsw{q}\t$dst", [], IIC_SMSW>, TB;
|
||||
|
||||
// For memory operands, there is only a 16-bit form
|
||||
def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
|
||||
"smsw{w}\t$dst", []>, TB;
|
||||
"smsw{w}\t$dst", [], IIC_SMSW>, TB;
|
||||
|
||||
def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
|
||||
"lmsw{w}\t$src", []>, TB;
|
||||
"lmsw{w}\t$src", [], IIC_LMSW_MEM>, TB;
|
||||
def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
|
||||
"lmsw{w}\t$src", []>, TB;
|
||||
"lmsw{w}\t$src", [], IIC_LMSW_REG>, TB;
|
||||
|
||||
def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
|
||||
def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", [], IIC_CPUID>, TB;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Cache instructions
|
||||
def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
|
||||
def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", []>, TB;
|
||||
def INVD : I<0x08, RawFrm, (outs), (ins), "invd", [], IIC_INVD>, TB;
|
||||
def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [], IIC_INVD>, TB;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// XSAVE instructions
|
||||
|
||||
@ -299,6 +299,59 @@ def IIC_FXRSTOR : InstrItinClass;
|
||||
|
||||
def IIC_FXCH : InstrItinClass;
|
||||
|
||||
// System instructions
|
||||
def IIC_CPUID : InstrItinClass;
|
||||
def IIC_INT : InstrItinClass;
|
||||
def IIC_INT3 : InstrItinClass;
|
||||
def IIC_INVD : InstrItinClass;
|
||||
def IIC_INVLPG : InstrItinClass;
|
||||
def IIC_IRET : InstrItinClass;
|
||||
def IIC_HLT : InstrItinClass;
|
||||
def IIC_LXS : InstrItinClass;
|
||||
def IIC_LTR : InstrItinClass;
|
||||
def IIC_RDTSC : InstrItinClass;
|
||||
def IIC_RSM : InstrItinClass;
|
||||
def IIC_SIDT : InstrItinClass;
|
||||
def IIC_SGDT : InstrItinClass;
|
||||
def IIC_SLDT : InstrItinClass;
|
||||
def IIC_STR : InstrItinClass;
|
||||
def IIC_SWAPGS : InstrItinClass;
|
||||
def IIC_SYSCALL : InstrItinClass;
|
||||
def IIC_SYS_ENTER_EXIT : InstrItinClass;
|
||||
def IIC_IN_RR : InstrItinClass;
|
||||
def IIC_IN_RI : InstrItinClass;
|
||||
def IIC_OUT_RR : InstrItinClass;
|
||||
def IIC_OUT_IR : InstrItinClass;
|
||||
def IIC_INS : InstrItinClass;
|
||||
def IIC_MOV_REG_DR : InstrItinClass;
|
||||
def IIC_MOV_DR_REG : InstrItinClass;
|
||||
def IIC_MOV_REG_CR : InstrItinClass;
|
||||
def IIC_MOV_CR_REG : InstrItinClass;
|
||||
def IIC_MOV_REG_SR : InstrItinClass;
|
||||
def IIC_MOV_MEM_SR : InstrItinClass;
|
||||
def IIC_MOV_SR_REG : InstrItinClass;
|
||||
def IIC_MOV_SR_MEM : InstrItinClass;
|
||||
def IIC_LAR_RM : InstrItinClass;
|
||||
def IIC_LAR_RR : InstrItinClass;
|
||||
def IIC_LSL_RM : InstrItinClass;
|
||||
def IIC_LSL_RR : InstrItinClass;
|
||||
def IIC_LGDT : InstrItinClass;
|
||||
def IIC_LIDT : InstrItinClass;
|
||||
def IIC_LLDT_REG : InstrItinClass;
|
||||
def IIC_LLDT_MEM : InstrItinClass;
|
||||
def IIC_PUSH_CS : InstrItinClass;
|
||||
def IIC_PUSH_SR : InstrItinClass;
|
||||
def IIC_POP_SR : InstrItinClass;
|
||||
def IIC_POP_SR_SS : InstrItinClass;
|
||||
def IIC_VERR : InstrItinClass;
|
||||
def IIC_VERW_REG : InstrItinClass;
|
||||
def IIC_VERW_MEM : InstrItinClass;
|
||||
def IIC_WRMSR : InstrItinClass;
|
||||
def IIC_RDMSR : InstrItinClass;
|
||||
def IIC_RDPMC : InstrItinClass;
|
||||
def IIC_SMSW : InstrItinClass;
|
||||
def IIC_LMSW_REG : InstrItinClass;
|
||||
def IIC_LMSW_MEM : InstrItinClass;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Processor instruction itineraries.
|
||||
|
||||
@ -339,7 +339,73 @@ def AtomItineraries : ProcessorItineraries<
|
||||
InstrItinData<IIC_FCOMPP, [InstrStage<1, [Port1]>] >,
|
||||
InstrItinData<IIC_FXSAVE, [InstrStage<140, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_FXRSTOR, [InstrStage<141, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_FXCH, [InstrStage<1, [Port0], 0>, InstrStage<1, [Port1]>] >
|
||||
InstrItinData<IIC_FXCH, [InstrStage<1, [Port0], 0>, InstrStage<1, [Port1]>] >,
|
||||
|
||||
// System instructions
|
||||
InstrItinData<IIC_CPUID, [InstrStage<121, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_INT, [InstrStage<127, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_INT3, [InstrStage<130, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_INVD, [InstrStage<1003, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_INVLPG, [InstrStage<71, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_IRET, [InstrStage<109, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_HLT, [InstrStage<121, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_LXS, [InstrStage<10, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_LTR, [InstrStage<83, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_RDTSC, [InstrStage<30, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_RSM, [InstrStage<741, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_SIDT, [InstrStage<4, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_SGDT, [InstrStage<4, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_SLDT, [InstrStage<3, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_STR, [InstrStage<3, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_SWAPGS, [InstrStage<22, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_SYSCALL, [InstrStage<96, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_SYS_ENTER_EXIT, [InstrStage<88, [Port0, Port1]>] >,
|
||||
|
||||
InstrItinData<IIC_IN_RR, [InstrStage<94, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_IN_RI, [InstrStage<92, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_OUT_RR, [InstrStage<68, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_OUT_IR, [InstrStage<72, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_INS, [InstrStage<59, [Port0, Port1]>] >,
|
||||
|
||||
InstrItinData<IIC_MOV_REG_DR, [InstrStage<88, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_MOV_DR_REG, [InstrStage<123, [Port0, Port1]>] >,
|
||||
// worst case for mov REG_CRx
|
||||
InstrItinData<IIC_MOV_REG_CR, [InstrStage<12, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_MOV_CR_REG, [InstrStage<136, [Port0, Port1]>] >,
|
||||
|
||||
InstrItinData<IIC_MOV_REG_SR, [InstrStage<1, [Port0]>] >,
|
||||
InstrItinData<IIC_MOV_MEM_SR, [InstrStage<2, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_MOV_SR_REG, [InstrStage<21, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_MOV_SR_MEM, [InstrStage<26, [Port0, Port1]>] >,
|
||||
// LAR
|
||||
InstrItinData<IIC_LAR_RM, [InstrStage<50, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_LAR_RR, [InstrStage<54, [Port0, Port1]>] >,
|
||||
// LSL
|
||||
InstrItinData<IIC_LSL_RM, [InstrStage<46, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_LSL_RR, [InstrStage<49, [Port0, Port1]>] >,
|
||||
|
||||
InstrItinData<IIC_LGDT, [InstrStage<44, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_LIDT, [InstrStage<44, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_LLDT_REG, [InstrStage<60, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_LLDT_MEM, [InstrStage<64, [Port0, Port1]>] >,
|
||||
// push control register, segment registers
|
||||
InstrItinData<IIC_PUSH_CS, [InstrStage<2, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_PUSH_SR, [InstrStage<2, [Port0, Port1]>] >,
|
||||
// pop control register, segment registers
|
||||
InstrItinData<IIC_POP_SR, [InstrStage<29, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_POP_SR_SS, [InstrStage<48, [Port0, Port1]>] >,
|
||||
// VERR, VERW
|
||||
InstrItinData<IIC_VERR, [InstrStage<41, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_VERW_REG, [InstrStage<51, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_VERW_MEM, [InstrStage<50, [Port0, Port1]>] >,
|
||||
// WRMSR, RDMSR
|
||||
InstrItinData<IIC_WRMSR, [InstrStage<202, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_RDMSR, [InstrStage<78, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_RDPMC, [InstrStage<46, [Port0, Port1]>] >,
|
||||
// SMSW, LMSW
|
||||
InstrItinData<IIC_SMSW, [InstrStage<9, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_LMSW_REG, [InstrStage<69, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_LMSW_MEM, [InstrStage<67, [Port0, Port1]>] >
|
||||
|
||||
]>;
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user