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Propagate more debug loc infos. This also includes some code cleaning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65207 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -728,12 +728,14 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
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bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
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!Fn->doesNotThrow() ||
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UnwindTablesMandatory;
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DebugLoc DL = DebugLoc::getUnknownLoc();
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DebugLoc DL = MBBI->getDebugLoc();
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// Prepare for frame info.
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unsigned FrameLabelId = 0;
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// Get the number of bytes to allocate from the FrameInfo.
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uint64_t StackSize = MFI->getStackSize();
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// Get desired stack alignment
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uint64_t MaxAlign = MFI->getMaxAlignment();
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@ -812,8 +814,9 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
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// The EFLAGS implicit def is dead.
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MI->getOperand(3).setIsDead();
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}
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} else
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} else {
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NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
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}
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unsigned ReadyLabelId = 0;
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if (needsFrameMoves) {
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@ -828,6 +831,9 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
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MBBI->getOpcode() == X86::PUSH64r))
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++MBBI;
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if (MBBI != MBB.end())
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DL = MBBI->getDebugLoc();
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if (NumBytes) { // adjust stack pointer: ESP -= numbytes
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if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
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// Check, whether EAX is livein for this function
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@ -845,7 +851,8 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
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// necessary to ensure that the guard pages used by the OS virtual memory
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// manager are allocated in correct sequence.
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if (!isEAXAlive) {
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BuildMI(MBB, MBBI,DL, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
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BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
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.addImm(NumBytes);
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BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
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.addExternalSymbol("_alloca");
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} else {
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@ -921,7 +928,7 @@ void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
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NumBytes = FrameSize - CSSize;
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// pop EBP.
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BuildMI(MBB, MBBI, DL,
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BuildMI(MBB, MBBI, DL,
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TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
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} else {
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NumBytes = StackSize - CSSize;
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@ -938,6 +945,8 @@ void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
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--MBBI;
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}
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DL = MBBI->getDebugLoc();
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// If there is an ADD32ri or SUB32ri of ESP immediately before this
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// instruction, merge the two instructions.
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if (NumBytes || MFI->hasVarSizedObjects())
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@ -997,19 +1006,22 @@ void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
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// Incoporate the retaddr area.
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Offset = StackAdj-MaxTCDelta;
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assert(Offset >= 0 && "Offset should never be negative");
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if (Offset) {
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// Check for possible merge with preceeding ADD instruction.
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Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
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emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
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}
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// Jump to label or value in register.
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if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
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BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPd)).
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addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
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else if (RetOpcode== X86::TCRETURNri64) {
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else if (RetOpcode== X86::TCRETURNri64)
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BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
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} else
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else
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BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr), JumpTarget.getReg());
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// Delete the pseudo instruction TCRETURN.
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MBB.erase(MBBI);
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} else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
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