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[FastISel][AArch64] Add branch weights.
Add branch weights to branch instructions, so that the following passes can optimize based on it (i.e. basic block ordering). Fixes <rdar://problem/17887137>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214537 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -17,6 +17,7 @@
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#include "AArch64Subtarget.h"
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#include "AArch64TargetMachine.h"
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#include "MCTargetDesc/AArch64AddressingModes.h"
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#include "llvm/Analysis/BranchProbabilityInfo.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/FastISel.h"
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#include "llvm/CodeGen/FunctionLoweringInfo.h"
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@ -843,7 +844,13 @@ bool AArch64FastISel::SelectBranch(const Instruction *I) {
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
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.addImm(CC)
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.addMBB(TBB);
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FuncInfo.MBB->addSuccessor(TBB);
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// Obtain the branch weight and add the TrueBB to the successor list.
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uint32_t BranchWeight = 0;
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if (FuncInfo.BPI)
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BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
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TBB->getBasicBlock());
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FuncInfo.MBB->addSuccessor(TBB, BranchWeight);
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FastEmitBranch(FBB, DbgLoc);
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return true;
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@ -881,7 +888,14 @@ bool AArch64FastISel::SelectBranch(const Instruction *I) {
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
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.addImm(CC)
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.addMBB(TBB);
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FuncInfo.MBB->addSuccessor(TBB);
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// Obtain the branch weight and add the TrueBB to the successor list.
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uint32_t BranchWeight = 0;
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if (FuncInfo.BPI)
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BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
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TBB->getBasicBlock());
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FuncInfo.MBB->addSuccessor(TBB, BranchWeight);
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FastEmitBranch(FBB, DbgLoc);
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return true;
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}
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@ -891,7 +905,13 @@ bool AArch64FastISel::SelectBranch(const Instruction *I) {
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MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::B))
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.addMBB(Target);
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FuncInfo.MBB->addSuccessor(Target);
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// Obtain the branch weight and add the target to the successor list.
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uint32_t BranchWeight = 0;
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if (FuncInfo.BPI)
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BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
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Target->getBasicBlock());
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FuncInfo.MBB->addSuccessor(Target, BranchWeight);
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return true;
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} else if (foldXALUIntrinsic(CC, I, BI->getCondition())) {
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// Fake request the condition, otherwise the intrinsic might be completely
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@ -904,7 +924,13 @@ bool AArch64FastISel::SelectBranch(const Instruction *I) {
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
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.addImm(CC)
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.addMBB(TBB);
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FuncInfo.MBB->addSuccessor(TBB);
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// Obtain the branch weight and add the TrueBB to the successor list.
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uint32_t BranchWeight = 0;
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if (FuncInfo.BPI)
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BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
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TBB->getBasicBlock());
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FuncInfo.MBB->addSuccessor(TBB, BranchWeight);
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FastEmitBranch(FBB, DbgLoc);
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return true;
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@ -935,7 +961,14 @@ bool AArch64FastISel::SelectBranch(const Instruction *I) {
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
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.addImm(CC)
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.addMBB(TBB);
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FuncInfo.MBB->addSuccessor(TBB);
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// Obtain the branch weight and add the TrueBB to the successor list.
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uint32_t BranchWeight = 0;
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if (FuncInfo.BPI)
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BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
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TBB->getBasicBlock());
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FuncInfo.MBB->addSuccessor(TBB, BranchWeight);
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FastEmitBranch(FBB, DbgLoc);
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return true;
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}
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19
test/CodeGen/AArch64/fast-isel-branch_weights.ll
Normal file
19
test/CodeGen/AArch64/fast-isel-branch_weights.ll
Normal file
@ -0,0 +1,19 @@
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; RUN: llc -mtriple=arm64-apple-darwin -aarch64-atomic-cfg-tidy=0 < %s | FileCheck %s
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; RUN: llc -mtriple=arm64-apple-darwin -aarch64-atomic-cfg-tidy=0 -fast-isel -fast-isel-abort < %s | FileCheck %s
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; Test if the BBs are reordred according to their branch weights.
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define i64 @branch_weights_test(i64 %a, i64 %b) {
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; CHECK-LABEL: branch_weights_test
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; CHECK-LABEL: success
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; CHECK-LABEL: fail
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%1 = icmp ult i64 %a, %b
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br i1 %1, label %fail, label %success, !prof !0
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fail:
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ret i64 -1
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success:
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ret i64 0
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}
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!0 = metadata !{metadata !"branch_weights", i32 0, i32 2147483647}
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