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[C++11] Add 'override' keyword to virtual methods that override their base class.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203439 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2014-03-10 03:19:03 +00:00
parent 673fbf14a6
commit 3d3e407e5f
10 changed files with 110 additions and 111 deletions
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36
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@ -359,20 +359,22 @@ public:
} }
// Implementation of the MCTargetAsmParser interface: // Implementation of the MCTargetAsmParser interface:
bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, bool
SMLoc NameLoc, ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
SmallVectorImpl<MCParsedAsmOperand*> &Operands); SMLoc NameLoc,
bool ParseDirective(AsmToken DirectiveID); SmallVectorImpl<MCParsedAsmOperand*> &Operands) override;
bool ParseDirective(AsmToken DirectiveID) override;
unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind); unsigned validateTargetOperandClass(MCParsedAsmOperand *Op,
unsigned checkTargetMatchPredicate(MCInst &Inst); unsigned Kind) override;
unsigned checkTargetMatchPredicate(MCInst &Inst) override;
bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
SmallVectorImpl<MCParsedAsmOperand*> &Operands, SmallVectorImpl<MCParsedAsmOperand*> &Operands,
MCStreamer &Out, unsigned &ErrorInfo, MCStreamer &Out, unsigned &ErrorInfo,
bool MatchingInlineAsm); bool MatchingInlineAsm) override;
void onLabelParsed(MCSymbol *Symbol); void onLabelParsed(MCSymbol *Symbol) override;
}; };
} // end anonymous namespace } // end anonymous namespace
@ -621,9 +623,9 @@ public:
} }
/// getStartLoc - Get the location of the first token of this operand. /// getStartLoc - Get the location of the first token of this operand.
SMLoc getStartLoc() const { return StartLoc; } SMLoc getStartLoc() const override { return StartLoc; }
/// getEndLoc - Get the location of the last token of this operand. /// getEndLoc - Get the location of the last token of this operand.
SMLoc getEndLoc() const { return EndLoc; } SMLoc getEndLoc() const override { return EndLoc; }
/// getLocRange - Get the range between the first and last token of this /// getLocRange - Get the range between the first and last token of this
/// operand. /// operand.
SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
@ -643,7 +645,7 @@ public:
return StringRef(Tok.Data, Tok.Length); return StringRef(Tok.Data, Tok.Length);
} }
unsigned getReg() const { unsigned getReg() const override {
assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!"); assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
return Reg.RegNum; return Reg.RegNum;
} }
@ -691,7 +693,7 @@ public:
bool isCCOut() const { return Kind == k_CCOut; } bool isCCOut() const { return Kind == k_CCOut; }
bool isITMask() const { return Kind == k_ITCondMask; } bool isITMask() const { return Kind == k_ITCondMask; }
bool isITCondCode() const { return Kind == k_CondCode; } bool isITCondCode() const { return Kind == k_CondCode; }
bool isImm() const { return Kind == k_Immediate; } bool isImm() const override { return Kind == k_Immediate; }
// checks whether this operand is an unsigned offset which fits is a field // checks whether this operand is an unsigned offset which fits is a field
// of specified width and scaled by a specific number of bits // of specified width and scaled by a specific number of bits
template<unsigned width, unsigned scale> template<unsigned width, unsigned scale>
@ -1067,14 +1069,14 @@ public:
int64_t Value = CE->getValue(); int64_t Value = CE->getValue();
return Value == 1 || Value == 0; return Value == 1 || Value == 0;
} }
bool isReg() const { return Kind == k_Register; } bool isReg() const override { return Kind == k_Register; }
bool isRegList() const { return Kind == k_RegisterList; } bool isRegList() const { return Kind == k_RegisterList; }
bool isDPRRegList() const { return Kind == k_DPRRegisterList; } bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
bool isSPRRegList() const { return Kind == k_SPRRegisterList; } bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
bool isToken() const { return Kind == k_Token; } bool isToken() const override { return Kind == k_Token; }
bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; } bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; } bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
bool isMem() const { return Kind == k_Memory; } bool isMem() const override { return Kind == k_Memory; }
bool isShifterImm() const { return Kind == k_ShifterImmediate; } bool isShifterImm() const { return Kind == k_ShifterImmediate; }
bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; } bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; } bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
@ -2309,7 +2311,7 @@ public:
Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00)); Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
} }
virtual void print(raw_ostream &OS) const; void print(raw_ostream &OS) const override;
static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) { static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
ARMOperand *Op = new ARMOperand(k_ITCondMask); ARMOperand *Op = new ARMOperand(k_ITCondMask);

16
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -98,12 +98,10 @@ public:
} }
/// getInstruction - See MCDisassembler. /// getInstruction - See MCDisassembler.
DecodeStatus getInstruction(MCInst &instr, DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
uint64_t &size, const MemoryObject &region, uint64_t address,
const MemoryObject &region,
uint64_t address,
raw_ostream &vStream, raw_ostream &vStream,
raw_ostream &cStream) const; raw_ostream &cStream) const override;
}; };
/// ThumbDisassembler - Thumb disassembler for all Thumb platforms. /// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
@ -119,12 +117,10 @@ public:
} }
/// getInstruction - See MCDisassembler. /// getInstruction - See MCDisassembler.
DecodeStatus getInstruction(MCInst &instr, DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
uint64_t &size, const MemoryObject &region, uint64_t address,
const MemoryObject &region,
uint64_t address,
raw_ostream &vStream, raw_ostream &vStream,
raw_ostream &cStream) const; raw_ostream &cStream) const override;
private: private:
mutable ITStatus ITBlock; mutable ITStatus ITBlock;

27
lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
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@ -51,13 +51,15 @@ public:
delete STI; delete STI;
} }
unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; } unsigned getNumFixupKinds() const override {
return ARM::NumTargetFixupKinds;
}
bool hasNOP() const { bool hasNOP() const {
return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0; return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0;
} }
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
const static MCFixupKindInfo Infos[ARM::NumTargetFixupKinds] = { const static MCFixupKindInfo Infos[ARM::NumTargetFixupKinds] = {
// This table *must* be in the order that the fixup_* kinds are defined in // This table *must* be in the order that the fixup_* kinds are defined in
// ARMFixupKinds.h. // ARMFixupKinds.h.
@ -113,24 +115,23 @@ public:
void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout, void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
const MCFixup &Fixup, const MCFragment *DF, const MCFixup &Fixup, const MCFragment *DF,
MCValue &Target, uint64_t &Value, MCValue &Target, uint64_t &Value,
bool &IsResolved); bool &IsResolved) override;
void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
uint64_t Value) const; uint64_t Value) const override;
bool mayNeedRelaxation(const MCInst &Inst) const; bool mayNeedRelaxation(const MCInst &Inst) const override;
bool fixupNeedsRelaxation(const MCFixup &Fixup, bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
uint64_t Value,
const MCRelaxableFragment *DF, const MCRelaxableFragment *DF,
const MCAsmLayout &Layout) const; const MCAsmLayout &Layout) const override;
void relaxInstruction(const MCInst &Inst, MCInst &Res) const; void relaxInstruction(const MCInst &Inst, MCInst &Res) const override;
bool writeNopData(uint64_t Count, MCObjectWriter *OW) const; bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
void handleAssemblerFlag(MCAssemblerFlag Flag) { void handleAssemblerFlag(MCAssemblerFlag Flag) override {
switch (Flag) { switch (Flag) {
default: break; default: break;
case MCAF_Code16: case MCAF_Code16:
@ -663,7 +664,7 @@ public:
uint8_t _OSABI) uint8_t _OSABI)
: ARMAsmBackend(T, TT), OSABI(_OSABI) { } : ARMAsmBackend(T, TT), OSABI(_OSABI) { }
MCObjectWriter *createObjectWriter(raw_ostream &OS) const { MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
return createARMELFObjectWriter(OS, OSABI); return createARMELFObjectWriter(OS, OSABI);
} }
}; };
@ -678,7 +679,7 @@ public:
HasDataInCodeSupport = true; HasDataInCodeSupport = true;
} }
MCObjectWriter *createObjectWriter(raw_ostream &OS) const { MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
return createARMMachObjectWriter(OS, /*Is64Bit=*/false, return createARMMachObjectWriter(OS, /*Is64Bit=*/false,
MachO::CPU_TYPE_ARM, MachO::CPU_TYPE_ARM,
Subtype); Subtype);

13
lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
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@ -34,14 +34,13 @@ namespace {
virtual ~ARMELFObjectWriter(); virtual ~ARMELFObjectWriter();
virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup,
bool IsPCRel, bool IsRelocWithSymbol, bool IsPCRel, bool IsRelocWithSymbol,
int64_t Addend) const; int64_t Addend) const override;
virtual const MCSymbol *ExplicitRelSym(const MCAssembler &Asm, const MCSymbol *ExplicitRelSym(const MCAssembler &Asm,
const MCValue &Target, const MCValue &Target, const MCFragment &F,
const MCFragment &F,
const MCFixup &Fixup, const MCFixup &Fixup,
bool IsPCRel) const; bool IsPCRel) const override;
}; };
} }

113
lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
View File

@ -114,32 +114,32 @@ class ARMTargetAsmStreamer : public ARMTargetStreamer {
MCInstPrinter &InstPrinter; MCInstPrinter &InstPrinter;
bool IsVerboseAsm; bool IsVerboseAsm;
virtual void emitFnStart(); void emitFnStart() override;
virtual void emitFnEnd(); void emitFnEnd() override;
virtual void emitCantUnwind(); void emitCantUnwind() override;
virtual void emitPersonality(const MCSymbol *Personality); void emitPersonality(const MCSymbol *Personality) override;
virtual void emitPersonalityIndex(unsigned Index); void emitPersonalityIndex(unsigned Index) override;
virtual void emitHandlerData(); void emitHandlerData() override;
virtual void emitSetFP(unsigned FpReg, unsigned SpReg, int64_t Offset = 0); void emitSetFP(unsigned FpReg, unsigned SpReg, int64_t Offset = 0) override;
virtual void emitMovSP(unsigned Reg, int64_t Offset = 0); void emitMovSP(unsigned Reg, int64_t Offset = 0) override;
virtual void emitPad(int64_t Offset); void emitPad(int64_t Offset) override;
virtual void emitRegSave(const SmallVectorImpl<unsigned> &RegList, void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
bool isVector); bool isVector) override;
virtual void emitUnwindRaw(int64_t Offset, void emitUnwindRaw(int64_t Offset,
const SmallVectorImpl<uint8_t> &Opcodes); const SmallVectorImpl<uint8_t> &Opcodes) override;
virtual void switchVendor(StringRef Vendor); void switchVendor(StringRef Vendor) override;
virtual void emitAttribute(unsigned Attribute, unsigned Value); void emitAttribute(unsigned Attribute, unsigned Value) override;
virtual void emitTextAttribute(unsigned Attribute, StringRef String); void emitTextAttribute(unsigned Attribute, StringRef String) override;
virtual void emitIntTextAttribute(unsigned Attribute, unsigned IntValue, void emitIntTextAttribute(unsigned Attribute, unsigned IntValue,
StringRef StrinValue); StringRef StrinValue) override;
virtual void emitArch(unsigned Arch); void emitArch(unsigned Arch) override;
virtual void emitObjectArch(unsigned Arch); void emitObjectArch(unsigned Arch) override;
virtual void emitFPU(unsigned FPU); void emitFPU(unsigned FPU) override;
virtual void emitInst(uint32_t Inst, char Suffix = '\0'); void emitInst(uint32_t Inst, char Suffix = '\0') override;
virtual void finishAttributeSection(); void finishAttributeSection() override;
virtual void AnnotateTLSDescriptorSequence(const MCSymbolRefExpr *SRE); void AnnotateTLSDescriptorSequence(const MCSymbolRefExpr *SRE) override;
public: public:
ARMTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS, ARMTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS,
@ -383,32 +383,32 @@ private:
ARMELFStreamer &getStreamer(); ARMELFStreamer &getStreamer();
virtual void emitFnStart(); void emitFnStart() override;
virtual void emitFnEnd(); void emitFnEnd() override;
virtual void emitCantUnwind(); void emitCantUnwind() override;
virtual void emitPersonality(const MCSymbol *Personality); void emitPersonality(const MCSymbol *Personality) override;
virtual void emitPersonalityIndex(unsigned Index); void emitPersonalityIndex(unsigned Index) override;
virtual void emitHandlerData(); void emitHandlerData() override;
virtual void emitSetFP(unsigned FpReg, unsigned SpReg, int64_t Offset = 0); void emitSetFP(unsigned FpReg, unsigned SpReg, int64_t Offset = 0) override;
virtual void emitMovSP(unsigned Reg, int64_t Offset = 0); void emitMovSP(unsigned Reg, int64_t Offset = 0) override;
virtual void emitPad(int64_t Offset); void emitPad(int64_t Offset) override;
virtual void emitRegSave(const SmallVectorImpl<unsigned> &RegList, void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
bool isVector); bool isVector) override;
virtual void emitUnwindRaw(int64_t Offset, void emitUnwindRaw(int64_t Offset,
const SmallVectorImpl<uint8_t> &Opcodes); const SmallVectorImpl<uint8_t> &Opcodes) override;
virtual void switchVendor(StringRef Vendor); void switchVendor(StringRef Vendor) override;
virtual void emitAttribute(unsigned Attribute, unsigned Value); void emitAttribute(unsigned Attribute, unsigned Value) override;
virtual void emitTextAttribute(unsigned Attribute, StringRef String); void emitTextAttribute(unsigned Attribute, StringRef String) override;
virtual void emitIntTextAttribute(unsigned Attribute, unsigned IntValue, void emitIntTextAttribute(unsigned Attribute, unsigned IntValue,
StringRef StringValue); StringRef StringValue) override;
virtual void emitArch(unsigned Arch); void emitArch(unsigned Arch) override;
virtual void emitObjectArch(unsigned Arch); void emitObjectArch(unsigned Arch) override;
virtual void emitFPU(unsigned FPU); void emitFPU(unsigned FPU) override;
virtual void emitInst(uint32_t Inst, char Suffix = '\0'); void emitInst(uint32_t Inst, char Suffix = '\0') override;
virtual void finishAttributeSection(); void finishAttributeSection() override;
virtual void AnnotateTLSDescriptorSequence(const MCSymbolRefExpr *SRE); void AnnotateTLSDescriptorSequence(const MCSymbolRefExpr *SRE) override;
size_t calculateContentSize() const; size_t calculateContentSize() const;
@ -444,7 +444,7 @@ public:
~ARMELFStreamer() {} ~ARMELFStreamer() {}
virtual void FinishImpl(); void FinishImpl() override;
// ARM exception handling directives // ARM exception handling directives
void emitFnStart(); void emitFnStart();
@ -459,8 +459,8 @@ public:
void emitRegSave(const SmallVectorImpl<unsigned> &RegList, bool isVector); void emitRegSave(const SmallVectorImpl<unsigned> &RegList, bool isVector);
void emitUnwindRaw(int64_t Offset, const SmallVectorImpl<uint8_t> &Opcodes); void emitUnwindRaw(int64_t Offset, const SmallVectorImpl<uint8_t> &Opcodes);
virtual void ChangeSection(const MCSection *Section, void ChangeSection(const MCSection *Section,
const MCExpr *Subsection) { const MCExpr *Subsection) override {
// We have to keep track of the mapping symbol state of any sections we // We have to keep track of the mapping symbol state of any sections we
// use. Each one should start off as EMS_None, which is provided as the // use. Each one should start off as EMS_None, which is provided as the
// default constructor by DenseMap::lookup. // default constructor by DenseMap::lookup.
@ -473,7 +473,8 @@ public:
/// This function is the one used to emit instruction data into the ELF /// This function is the one used to emit instruction data into the ELF
/// streamer. We override it to add the appropriate mapping symbol if /// streamer. We override it to add the appropriate mapping symbol if
/// necessary. /// necessary.
virtual void EmitInstruction(const MCInst& Inst, const MCSubtargetInfo &STI) { void EmitInstruction(const MCInst& Inst,
const MCSubtargetInfo &STI) override {
if (IsThumb) if (IsThumb)
EmitThumbMappingSymbol(); EmitThumbMappingSymbol();
else else
@ -523,7 +524,7 @@ public:
/// This is one of the functions used to emit data into an ELF section, so the /// This is one of the functions used to emit data into an ELF section, so the
/// ARM streamer overrides it to add the appropriate mapping symbol ($d) if /// ARM streamer overrides it to add the appropriate mapping symbol ($d) if
/// necessary. /// necessary.
virtual void EmitBytes(StringRef Data) { void EmitBytes(StringRef Data) override {
EmitDataMappingSymbol(); EmitDataMappingSymbol();
MCELFStreamer::EmitBytes(Data); MCELFStreamer::EmitBytes(Data);
} }
@ -531,12 +532,12 @@ public:
/// This is one of the functions used to emit data into an ELF section, so the /// This is one of the functions used to emit data into an ELF section, so the
/// ARM streamer overrides it to add the appropriate mapping symbol ($d) if /// ARM streamer overrides it to add the appropriate mapping symbol ($d) if
/// necessary. /// necessary.
virtual void EmitValueImpl(const MCExpr *Value, unsigned Size) { void EmitValueImpl(const MCExpr *Value, unsigned Size) override {
EmitDataMappingSymbol(); EmitDataMappingSymbol();
MCELFStreamer::EmitValueImpl(Value, Size); MCELFStreamer::EmitValueImpl(Value, Size);
} }
virtual void EmitAssemblerFlag(MCAssemblerFlag Flag) { void EmitAssemblerFlag(MCAssemblerFlag Flag) override {
MCELFStreamer::EmitAssemblerFlag(Flag); MCELFStreamer::EmitAssemblerFlag(Flag);
switch (Flag) { switch (Flag) {
@ -599,7 +600,7 @@ private:
Symbol->setVariableValue(Value); Symbol->setVariableValue(Value);
} }
void EmitThumbFunc(MCSymbol *Func) { void EmitThumbFunc(MCSymbol *Func) override {
// FIXME: Anything needed here to flag the function as thumb? // FIXME: Anything needed here to flag the function as thumb?
getAssembler().setIsThumbFunc(Func); getAssembler().setIsThumbFunc(Func);

4
lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h
View File

@ -20,13 +20,13 @@
namespace llvm { namespace llvm {
class ARMMCAsmInfoDarwin : public MCAsmInfoDarwin { class ARMMCAsmInfoDarwin : public MCAsmInfoDarwin {
virtual void anchor(); void anchor() override;
public: public:
explicit ARMMCAsmInfoDarwin(); explicit ARMMCAsmInfoDarwin();
}; };
class ARMELFMCAsmInfo : public MCAsmInfoELF { class ARMELFMCAsmInfo : public MCAsmInfoELF {
virtual void anchor(); void anchor() override;
public: public:
explicit ARMELFMCAsmInfo(); explicit ARMELFMCAsmInfo();
}; };

2
lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
View File

@ -392,7 +392,7 @@ public:
void EncodeInstruction(const MCInst &MI, raw_ostream &OS, void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const; const MCSubtargetInfo &STI) const override;
}; };
} // end anonymous namespace } // end anonymous namespace

6
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
View File

@ -287,14 +287,14 @@ class ARMMCInstrAnalysis : public MCInstrAnalysis {
public: public:
ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {} ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
virtual bool isUnconditionalBranch(const MCInst &Inst) const { bool isUnconditionalBranch(const MCInst &Inst) const override {
// BCCs with the "always" predicate are unconditional branches. // BCCs with the "always" predicate are unconditional branches.
if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL) if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
return true; return true;
return MCInstrAnalysis::isUnconditionalBranch(Inst); return MCInstrAnalysis::isUnconditionalBranch(Inst);
} }
virtual bool isConditionalBranch(const MCInst &Inst) const { bool isConditionalBranch(const MCInst &Inst) const override {
// BCCs with the "always" predicate are unconditional branches. // BCCs with the "always" predicate are unconditional branches.
if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL) if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
return false; return false;
@ -302,7 +302,7 @@ public:
} }
bool evaluateBranch(const MCInst &Inst, uint64_t Addr, bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
uint64_t Size, uint64_t &Target) const { uint64_t Size, uint64_t &Target) const override {
// We only handle PCRel branches for now. // We only handle PCRel branches for now.
if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL) if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
return false; return false;

2
lib/Target/ARM/MCTargetDesc/ARMMachORelocationInfo.cpp
View File

@ -23,7 +23,7 @@ public:
ARMMachORelocationInfo(MCContext &Ctx) : MCRelocationInfo(Ctx) {} ARMMachORelocationInfo(MCContext &Ctx) : MCRelocationInfo(Ctx) {}
const MCExpr *createExprForCAPIVariantKind(const MCExpr *SubExpr, const MCExpr *createExprForCAPIVariantKind(const MCExpr *SubExpr,
unsigned VariantKind) { unsigned VariantKind) override {
switch(VariantKind) { switch(VariantKind) {
case LLVMDisassembler_VariantKind_ARM_HI16: case LLVMDisassembler_VariantKind_ARM_HI16:
return ARMMCExpr::CreateUpper16(SubExpr, Ctx); return ARMMCExpr::CreateUpper16(SubExpr, Ctx);

2
lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
View File

@ -56,7 +56,7 @@ public:
void RecordRelocation(MachObjectWriter *Writer, void RecordRelocation(MachObjectWriter *Writer,
const MCAssembler &Asm, const MCAsmLayout &Layout, const MCAssembler &Asm, const MCAsmLayout &Layout,
const MCFragment *Fragment, const MCFixup &Fixup, const MCFragment *Fragment, const MCFixup &Fixup,
MCValue Target, uint64_t &FixedValue); MCValue Target, uint64_t &FixedValue) override;
}; };
} }