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Swift: Only build vldm/vstm with q register aligned register lists

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Unaligned vldm/vstm need more uops and therefore are slower in general on swift.

radar://14522102

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189961 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Arnold Schwaighofer
2013-09-04 17:41:16 +00:00
parent 87b120690b
commit 3d476a80e9
2 changed files with 32 additions and 1 deletions
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5
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
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@ -489,7 +489,10 @@ ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
if (Reg != ARM::SP &&
NewOffset == Offset + (int)Size &&
((isNotVFP && RegNum > PRegNum) ||
((Count < Limit) && RegNum == PRegNum+1))) {
((Count < Limit) && RegNum == PRegNum+1)) &&
// On Swift we don't want vldm/vstm to start with a odd register num
// because Q register unaligned vldm/vstm need more uops.
(!STI->isSwift() || isNotVFP || Count != 1 || !(PRegNum & 0x1))) {
Offset += Size;
PRegNum = RegNum;
++Count;