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AArch64: Add missing scalar pair intrinsics.
E.g. "float32_t vaddv_f32(float32x2_t a)" to be matched into "faddp s0, v1.2s". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196198 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hao Liu
parent
7af2eb1ab4
commit
3d69ff4d07
@ -5194,6 +5194,8 @@ defm ADDPvv : NeonI_ScalarPair_D_sizes<0b0, 0b1, 0b11011, "addp", 0>;
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// Scalar Reduce Addition Pairwise (Integer)
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def : Pat<(v1i64 (int_aarch64_neon_vpadd (v2i64 VPR128:$Rn))),
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(ADDPvv_D_2D VPR128:$Rn)>;
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def : Pat<(v1i64 (int_aarch64_neon_vaddv (v2i64 VPR128:$Rn))),
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(ADDPvv_D_2D VPR128:$Rn)>;
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// Scalar Reduce Addition Pairwise (Floating Point)
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defm FADDPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01101, "faddp", 0>;
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@ -5237,6 +5239,26 @@ defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfmaxnm,
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defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfminnm,
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int_aarch64_neon_vpfminnmq, FMINNMPvv_S_2S, FMINNMPvv_D_2D>;
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defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vaddv,
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int_aarch64_neon_vaddv, FADDPvv_S_2S, FADDPvv_D_2D>;
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def : Pat<(v1f32 (int_aarch64_neon_vaddv (v4f32 VPR128:$Rn))),
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(FADDPvv_S_2S (v2f32
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(EXTRACT_SUBREG
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(v4f32 (FADDP_4S (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rn))),
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sub_64)))>;
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defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vmaxv,
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int_aarch64_neon_vmaxv, FMAXPvv_S_2S, FMAXPvv_D_2D>;
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defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vminv,
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int_aarch64_neon_vminv, FMINPvv_S_2S, FMINPvv_D_2D>;
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defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vmaxnmv,
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int_aarch64_neon_vmaxnmv, FMAXNMPvv_S_2S, FMAXNMPvv_D_2D>;
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defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vminnmv,
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int_aarch64_neon_vminnmv, FMINNMPvv_S_2S, FMINNMPvv_D_2D>;
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// Scalar by element Arithmetic
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@ -101,3 +101,147 @@ define <1 x double> @test_fminnmp_v1f64(<2 x double> %a) {
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ret <1 x double> %val
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}
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define float @test_vaddv_f32(<2 x float> %a) {
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; CHECK-LABEL: test_vaddv_f32
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; CHECK: faddp {{s[0-9]+}}, {{v[0-9]+}}.2s
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%1 = tail call <1 x float> @llvm.aarch64.neon.vaddv.v1f32.v2f32(<2 x float> %a)
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%2 = extractelement <1 x float> %1, i32 0
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ret float %2
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}
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define float @test_vaddvq_f32(<4 x float> %a) {
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; CHECK-LABEL: test_vaddvq_f32
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; CHECK: faddp {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
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; CHECK: faddp {{s[0-9]+}}, {{v[0-9]+}}.2s
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%1 = tail call <1 x float> @llvm.aarch64.neon.vaddv.v1f32.v4f32(<4 x float> %a)
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%2 = extractelement <1 x float> %1, i32 0
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ret float %2
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}
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define double @test_vaddvq_f64(<2 x double> %a) {
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; CHECK-LABEL: test_vaddvq_f64
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; CHECK: faddp {{d[0-9]+}}, {{v[0-9]+}}.2d
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%1 = tail call <1 x double> @llvm.aarch64.neon.vaddv.v1f64.v2f64(<2 x double> %a)
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%2 = extractelement <1 x double> %1, i32 0
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ret double %2
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}
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define float @test_vmaxv_f32(<2 x float> %a) {
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; CHECK-LABEL: test_vmaxv_f32
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; CHECK: fmaxp {{s[0-9]+}}, {{v[0-9]+}}.2s
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%1 = tail call <1 x float> @llvm.aarch64.neon.vmaxv.v1f32.v2f32(<2 x float> %a)
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%2 = extractelement <1 x float> %1, i32 0
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ret float %2
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}
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define double @test_vmaxvq_f64(<2 x double> %a) {
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; CHECK-LABEL: test_vmaxvq_f64
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; CHECK: fmaxp {{d[0-9]+}}, {{v[0-9]+}}.2d
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%1 = tail call <1 x double> @llvm.aarch64.neon.vmaxv.v1f64.v2f64(<2 x double> %a)
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%2 = extractelement <1 x double> %1, i32 0
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ret double %2
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}
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define float @test_vminv_f32(<2 x float> %a) {
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; CHECK-LABEL: test_vminv_f32
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; CHECK: fminp {{s[0-9]+}}, {{v[0-9]+}}.2s
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%1 = tail call <1 x float> @llvm.aarch64.neon.vminv.v1f32.v2f32(<2 x float> %a)
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%2 = extractelement <1 x float> %1, i32 0
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ret float %2
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}
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define double @test_vminvq_f64(<2 x double> %a) {
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; CHECK-LABEL: test_vminvq_f64
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; CHECK: fminp {{d[0-9]+}}, {{v[0-9]+}}.2d
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%1 = tail call <1 x double> @llvm.aarch64.neon.vminv.v1f64.v2f64(<2 x double> %a)
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%2 = extractelement <1 x double> %1, i32 0
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ret double %2
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}
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define double @test_vmaxnmvq_f64(<2 x double> %a) {
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; CHECK-LABEL: test_vmaxnmvq_f64
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; CHECK: fmaxnmp {{d[0-9]+}}, {{v[0-9]+}}.2d
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%1 = tail call <1 x double> @llvm.aarch64.neon.vmaxnmv.v1f64.v2f64(<2 x double> %a)
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%2 = extractelement <1 x double> %1, i32 0
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ret double %2
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}
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define float @test_vmaxnmv_f32(<2 x float> %a) {
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; CHECK-LABEL: test_vmaxnmv_f32
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; CHECK: fmaxnmp {{s[0-9]+}}, {{v[0-9]+}}.2s
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%1 = tail call <1 x float> @llvm.aarch64.neon.vmaxnmv.v1f32.v2f32(<2 x float> %a)
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%2 = extractelement <1 x float> %1, i32 0
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ret float %2
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}
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define double @test_vminnmvq_f64(<2 x double> %a) {
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; CHECK-LABEL: test_vminnmvq_f64
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; CHECK: fminnmp {{d[0-9]+}}, {{v[0-9]+}}.2d
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%1 = tail call <1 x double> @llvm.aarch64.neon.vminnmv.v1f64.v2f64(<2 x double> %a)
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%2 = extractelement <1 x double> %1, i32 0
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ret double %2
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}
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define float @test_vminnmv_f32(<2 x float> %a) {
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; CHECK-LABEL: test_vminnmv_f32
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; CHECK: fminnmp {{s[0-9]+}}, {{v[0-9]+}}.2s
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%1 = tail call <1 x float> @llvm.aarch64.neon.vminnmv.v1f32.v2f32(<2 x float> %a)
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%2 = extractelement <1 x float> %1, i32 0
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ret float %2
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}
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define <2 x i64> @test_vpaddq_s64(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vpaddq_s64
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; CHECK: addp {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
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%1 = tail call <2 x i64> @llvm.arm.neon.vpadd.v2i64(<2 x i64> %a, <2 x i64> %b)
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ret <2 x i64> %1
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}
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define <2 x i64> @test_vpaddq_u64(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vpaddq_u64
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; CHECK: addp {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
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%1 = tail call <2 x i64> @llvm.arm.neon.vpadd.v2i64(<2 x i64> %a, <2 x i64> %b)
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ret <2 x i64> %1
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}
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define i64 @test_vaddvq_s64(<2 x i64> %a) {
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; CHECK-LABEL: test_vaddvq_s64
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; CHECK: addp {{d[0-9]+}}, {{v[0-9]+}}.2d
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%1 = tail call <1 x i64> @llvm.aarch64.neon.vaddv.v1i64.v2i64(<2 x i64> %a)
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%2 = extractelement <1 x i64> %1, i32 0
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ret i64 %2
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}
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define i64 @test_vaddvq_u64(<2 x i64> %a) {
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; CHECK-LABEL: test_vaddvq_u64
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; CHECK: addp {{d[0-9]+}}, {{v[0-9]+}}.2d
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%1 = tail call <1 x i64> @llvm.aarch64.neon.vaddv.v1i64.v2i64(<2 x i64> %a)
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%2 = extractelement <1 x i64> %1, i32 0
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ret i64 %2
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}
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declare <1 x i64> @llvm.aarch64.neon.vaddv.v1i64.v2i64(<2 x i64>)
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declare <2 x i64> @llvm.arm.neon.vpadd.v2i64(<2 x i64>, <2 x i64>)
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declare <1 x float> @llvm.aarch64.neon.vminnmv.v1f32.v2f32(<2 x float>)
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declare <1 x double> @llvm.aarch64.neon.vminnmv.v1f64.v2f64(<2 x double>)
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declare <1 x float> @llvm.aarch64.neon.vmaxnmv.v1f32.v2f32(<2 x float>)
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declare <1 x double> @llvm.aarch64.neon.vmaxnmv.v1f64.v2f64(<2 x double>)
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declare <1 x double> @llvm.aarch64.neon.vminv.v1f64.v2f64(<2 x double>)
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declare <1 x float> @llvm.aarch64.neon.vminv.v1f32.v2f32(<2 x float>)
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declare <1 x double> @llvm.aarch64.neon.vmaxv.v1f64.v2f64(<2 x double>)
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declare <1 x float> @llvm.aarch64.neon.vmaxv.v1f32.v2f32(<2 x float>)
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declare <1 x double> @llvm.aarch64.neon.vaddv.v1f64.v2f64(<2 x double>)
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declare <1 x float> @llvm.aarch64.neon.vaddv.v1f32.v4f32(<4 x float>)
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declare <1 x float> @llvm.aarch64.neon.vaddv.v1f32.v2f32(<2 x float>)
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