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These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt.  Also add two test cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128191 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2011-03-24 01:40:42 +00:00
parent 571f290376
commit 3d793962be
2 changed files with 10 additions and 4 deletions
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8
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
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@ -1235,13 +1235,13 @@ static bool DisassembleStMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
}
// The algorithm for disassembly of LdStMulFrm is different from others because
// it explicitly populates the two predicate operands after operand 0 (the base)
// and operand 1 (the AM4 mode imm). After operand 3, we need to populate the
// reglist with each affected register encoded as an MCOperand.
// it explicitly populates the two predicate operands after the base register.
// After that, we need to populate the reglist with each affected register
// encoded as an MCOperand.
static bool DisassembleLdStMulFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
assert(NumOps >= 5 && "LdStMulFrm expects NumOps >= 5");
assert(NumOps >= 4 && "LdStMulFrm expects NumOps >= 4");
NumOpsAdded = 0;
unsigned Base = getRegisterEnum(B, ARM::GPRRegClassID, decodeRn(insn));

6
test/MC/Disassembler/ARM/arm-tests.txt
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@ -175,3 +175,9 @@
# CHECK: strtvc r5, [r3], r0, lsr #20
0x30 0x5a 0xa3 0x76
# CHECK: stmiblo sp, {r0, r4, r8, r11, r12, pc}
0x11 0x99 0x8d 0x39
# CHECK: ldmdb sp, {r0, r4, r8, r11, r12, pc}
0x11 0x99 0x1d 0xe9