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Add scheduling information for the MBlaze backend.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129311 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Wesley Peck 2011-04-11 22:31:52 +00:00
parent 120fd2dd6d
commit 3d820baf19
18 changed files with 719 additions and 243 deletions
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27
lib/Target/MBlaze/MBlaze.td
View File

@ -31,49 +31,28 @@ def MBlazeInstrInfo : InstrInfo;
// Microblaze Subtarget features // // Microblaze Subtarget features //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def FeaturePipe3 : SubtargetFeature<"pipe3", "HasPipe3", "true",
"Implements 3-stage pipeline">;
def FeatureBarrel : SubtargetFeature<"barrel", "HasBarrel", "true", def FeatureBarrel : SubtargetFeature<"barrel", "HasBarrel", "true",
"Implements barrel shifter">; "Implements barrel shifter">;
def FeatureDiv : SubtargetFeature<"div", "HasDiv", "true", def FeatureDiv : SubtargetFeature<"div", "HasDiv", "true",
"Implements hardware divider">; "Implements hardware divider">;
def FeatureMul : SubtargetFeature<"mul", "HasMul", "true", def FeatureMul : SubtargetFeature<"mul", "HasMul", "true",
"Implements hardware multiplier">; "Implements hardware multiplier">;
def FeatureFSL : SubtargetFeature<"fsl", "HasFSL", "true",
"Implements FSL instructions">;
def FeatureEFSL : SubtargetFeature<"efsl", "HasEFSL", "true",
"Implements extended FSL instructions">;
def FeatureMSRSet : SubtargetFeature<"msrset", "HasMSRSet", "true",
"Implements MSR register set and clear">;
def FeatureException : SubtargetFeature<"exception", "HasException", "true",
"Implements hardware exception support">;
def FeaturePatCmp : SubtargetFeature<"patcmp", "HasPatCmp", "true", def FeaturePatCmp : SubtargetFeature<"patcmp", "HasPatCmp", "true",
"Implements pattern compare instruction">; "Implements pattern compare instruction">;
def FeatureFPU : SubtargetFeature<"fpu", "HasFPU", "true", def FeatureFPU : SubtargetFeature<"fpu", "HasFPU", "true",
"Implements floating point unit">; "Implements floating point unit">;
def FeatureESR : SubtargetFeature<"esr", "HasESR", "true",
"Implements ESR and EAR registers">;
def FeaturePVR : SubtargetFeature<"pvr", "HasPVR", "true",
"Implements processor version register">;
def FeatureMul64 : SubtargetFeature<"mul64", "HasMul64", "true", def FeatureMul64 : SubtargetFeature<"mul64", "HasMul64", "true",
"Implements multiplier with 64-bit result">; "Implements multiplier with 64-bit result">;
def FeatureSqrt : SubtargetFeature<"sqrt", "HasSqrt", "true", def FeatureSqrt : SubtargetFeature<"sqrt", "HasSqrt", "true",
"Implements sqrt and floating point convert">; "Implements sqrt and floating point convert">;
def FeatureMMU : SubtargetFeature<"mmu", "HasMMU", "true",
"Implements memory management unit">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// MBlaze processors supported. // MBlaze processors supported.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class Proc<string Name, list<SubtargetFeature> Features> def : Processor<"mblaze", MBlazeGenericItineraries, []>;
: Processor<Name, MBlazeGenericItineraries, Features>; def : Processor<"mblaze3", MBlazePipe3Itineraries, []>;
def : Processor<"mblaze5", MBlazePipe5Itineraries, []>;
def : Proc<"v400", []>;
def : Proc<"v500", []>;
def : Proc<"v600", []>;
def : Proc<"v700", []>;
def : Proc<"v710", []>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Instruction Descriptions // Instruction Descriptions

43
lib/Target/MBlaze/MBlazeInstrFPU.td
View File

@ -21,22 +21,22 @@
class LoadFM<bits<6> op, string instr_asm, PatFrag OpNode> : class LoadFM<bits<6> op, string instr_asm, PatFrag OpNode> :
TA<op, 0x000, (outs GPR:$dst), (ins memrr:$addr), TA<op, 0x000, (outs GPR:$dst), (ins memrr:$addr),
!strconcat(instr_asm, " $dst, $addr"), !strconcat(instr_asm, " $dst, $addr"),
[(set (f32 GPR:$dst), (OpNode xaddr:$addr))], IILoad>; [(set (f32 GPR:$dst), (OpNode xaddr:$addr))], IIC_MEMl>;
class LoadFMI<bits<6> op, string instr_asm, PatFrag OpNode> : class LoadFMI<bits<6> op, string instr_asm, PatFrag OpNode> :
TB<op, (outs GPR:$dst), (ins memri:$addr), TB<op, (outs GPR:$dst), (ins memri:$addr),
!strconcat(instr_asm, " $dst, $addr"), !strconcat(instr_asm, " $dst, $addr"),
[(set (f32 GPR:$dst), (OpNode iaddr:$addr))], IILoad>; [(set (f32 GPR:$dst), (OpNode iaddr:$addr))], IIC_MEMl>;
class StoreFM<bits<6> op, string instr_asm, PatFrag OpNode> : class StoreFM<bits<6> op, string instr_asm, PatFrag OpNode> :
TA<op, 0x000, (outs), (ins GPR:$dst, memrr:$addr), TA<op, 0x000, (outs), (ins GPR:$dst, memrr:$addr),
!strconcat(instr_asm, " $dst, $addr"), !strconcat(instr_asm, " $dst, $addr"),
[(OpNode (f32 GPR:$dst), xaddr:$addr)], IIStore>; [(OpNode (f32 GPR:$dst), xaddr:$addr)], IIC_MEMs>;
class StoreFMI<bits<6> op, string instr_asm, PatFrag OpNode> : class StoreFMI<bits<6> op, string instr_asm, PatFrag OpNode> :
TB<op, (outs), (ins GPR:$dst, memrr:$addr), TB<op, (outs), (ins GPR:$dst, memrr:$addr),
!strconcat(instr_asm, " $dst, $addr"), !strconcat(instr_asm, " $dst, $addr"),
[(OpNode (f32 GPR:$dst), iaddr:$addr)], IIStore>; [(OpNode (f32 GPR:$dst), iaddr:$addr)], IIC_MEMs>;
class ArithF<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode, class ArithF<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode,
InstrItinClass itin> : InstrItinClass itin> :
@ -56,15 +56,10 @@ class ArithFR<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode,
!strconcat(instr_asm, " $dst, $c, $b"), !strconcat(instr_asm, " $dst, $c, $b"),
[(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], itin>; [(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], itin>;
class LogicF<bits<6> op, string instr_asm> :
TB<op, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
!strconcat(instr_asm, " $dst, $b, $c"),
[], IIAlu>;
class LogicFI<bits<6> op, string instr_asm> : class LogicFI<bits<6> op, string instr_asm> :
TB<op, (outs GPR:$dst), (ins GPR:$b, fimm:$c), TB<op, (outs GPR:$dst), (ins GPR:$b, fimm:$c),
!strconcat(instr_asm, " $dst, $b, $c"), !strconcat(instr_asm, " $dst, $b, $c"),
[], IIAlu>; [], IIC_ALU>;
let rb=0 in { let rb=0 in {
class ArithF2<bits<6> op, bits<11> flags, string instr_asm, class ArithF2<bits<6> op, bits<11> flags, string instr_asm,
@ -95,10 +90,10 @@ let rb=0 in {
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let Predicates=[HasFPU] in { let Predicates=[HasFPU] in {
def FORI : LogicFI<0x28, "ori ">; def FORI : LogicFI<0x28, "ori ">;
def FADD : ArithF<0x16, 0x000, "fadd ", fadd, IIAlu>; def FADD : ArithF<0x16, 0x000, "fadd ", fadd, IIC_FPU>;
def FRSUB : ArithFR<0x16, 0x080, "frsub ", fsub, IIAlu>; def FRSUB : ArithFR<0x16, 0x080, "frsub ", fsub, IIC_FPU>;
def FMUL : ArithF<0x16, 0x100, "fmul ", fmul, IIAlu>; def FMUL : ArithF<0x16, 0x100, "fmul ", fmul, IIC_FPU>;
def FDIV : ArithF<0x16, 0x180, "fdiv ", fdiv, IIAlu>; def FDIV : ArithF<0x16, 0x180, "fdiv ", fdiv, IIC_FPUd>;
} }
let Predicates=[HasFPU], isCodeGenOnly=1 in { let Predicates=[HasFPU], isCodeGenOnly=1 in {
@ -110,19 +105,19 @@ let Predicates=[HasFPU], isCodeGenOnly=1 in {
} }
let Predicates=[HasFPU,HasSqrt] in { let Predicates=[HasFPU,HasSqrt] in {
def FLT : ArithIF<0x16, 0x280, "flt ", IIAlu>; def FLT : ArithIF<0x16, 0x280, "flt ", IIC_FPUf>;
def FINT : ArithFI<0x16, 0x300, "fint ", IIAlu>; def FINT : ArithFI<0x16, 0x300, "fint ", IIC_FPUi>;
def FSQRT : ArithF2<0x16, 0x380, "fsqrt ", IIAlu>; def FSQRT : ArithF2<0x16, 0x380, "fsqrt ", IIC_FPUs>;
} }
let isAsCheapAsAMove = 1 in { let isAsCheapAsAMove = 1 in {
def FCMP_UN : CmpFN<0x16, 0x200, "fcmp.un", IIAlu>; def FCMP_UN : CmpFN<0x16, 0x200, "fcmp.un", IIC_FPUc>;
def FCMP_LT : CmpFN<0x16, 0x210, "fcmp.lt", IIAlu>; def FCMP_LT : CmpFN<0x16, 0x210, "fcmp.lt", IIC_FPUc>;
def FCMP_EQ : CmpFN<0x16, 0x220, "fcmp.eq", IIAlu>; def FCMP_EQ : CmpFN<0x16, 0x220, "fcmp.eq", IIC_FPUc>;
def FCMP_LE : CmpFN<0x16, 0x230, "fcmp.le", IIAlu>; def FCMP_LE : CmpFN<0x16, 0x230, "fcmp.le", IIC_FPUc>;
def FCMP_GT : CmpFN<0x16, 0x240, "fcmp.gt", IIAlu>; def FCMP_GT : CmpFN<0x16, 0x240, "fcmp.gt", IIC_FPUc>;
def FCMP_NE : CmpFN<0x16, 0x250, "fcmp.ne", IIAlu>; def FCMP_NE : CmpFN<0x16, 0x250, "fcmp.ne", IIC_FPUc>;
def FCMP_GE : CmpFN<0x16, 0x260, "fcmp.ge", IIAlu>; def FCMP_GE : CmpFN<0x16, 0x260, "fcmp.ge", IIC_FPUc>;
} }

12
lib/Target/MBlaze/MBlazeInstrFSL.td
View File

@ -13,7 +13,7 @@
class FSLGet<bits<6> op, bits<5> flags, string instr_asm, Intrinsic OpNode> : class FSLGet<bits<6> op, bits<5> flags, string instr_asm, Intrinsic OpNode> :
MBlazeInst<op, FRCX, (outs GPR:$dst), (ins fslimm:$b), MBlazeInst<op, FRCX, (outs GPR:$dst), (ins fslimm:$b),
!strconcat(instr_asm, " $dst, $b"), !strconcat(instr_asm, " $dst, $b"),
[(set GPR:$dst, (OpNode immZExt4:$b))],IIAlu> [(set GPR:$dst, (OpNode immZExt4:$b))],IIC_FSLg>
{ {
bits<5> rd; bits<5> rd;
bits<4> fslno; bits<4> fslno;
@ -29,7 +29,7 @@ class FSLGet<bits<6> op, bits<5> flags, string instr_asm, Intrinsic OpNode> :
class FSLGetD<bits<6> op, bits<5> flags, string instr_asm, Intrinsic OpNode> : class FSLGetD<bits<6> op, bits<5> flags, string instr_asm, Intrinsic OpNode> :
MBlazeInst<op, FRCR, (outs GPR:$dst), (ins GPR:$b), MBlazeInst<op, FRCR, (outs GPR:$dst), (ins GPR:$b),
!strconcat(instr_asm, " $dst, $b"), !strconcat(instr_asm, " $dst, $b"),
[(set GPR:$dst, (OpNode GPR:$b))], IIAlu> [(set GPR:$dst, (OpNode GPR:$b))], IIC_FSLg>
{ {
bits<5> rd; bits<5> rd;
bits<5> rb; bits<5> rb;
@ -45,7 +45,7 @@ class FSLGetD<bits<6> op, bits<5> flags, string instr_asm, Intrinsic OpNode> :
class FSLPut<bits<6> op, bits<4> flags, string instr_asm, Intrinsic OpNode> : class FSLPut<bits<6> op, bits<4> flags, string instr_asm, Intrinsic OpNode> :
MBlazeInst<op, FCRCX, (outs), (ins GPR:$v, fslimm:$b), MBlazeInst<op, FCRCX, (outs), (ins GPR:$v, fslimm:$b),
!strconcat(instr_asm, " $v, $b"), !strconcat(instr_asm, " $v, $b"),
[(OpNode GPR:$v, immZExt4:$b)], IIAlu> [(OpNode GPR:$v, immZExt4:$b)], IIC_FSLp>
{ {
bits<5> ra; bits<5> ra;
bits<4> fslno; bits<4> fslno;
@ -61,7 +61,7 @@ class FSLPut<bits<6> op, bits<4> flags, string instr_asm, Intrinsic OpNode> :
class FSLPutD<bits<6> op, bits<4> flags, string instr_asm, Intrinsic OpNode> : class FSLPutD<bits<6> op, bits<4> flags, string instr_asm, Intrinsic OpNode> :
MBlazeInst<op, FCRR, (outs), (ins GPR:$v, GPR:$b), MBlazeInst<op, FCRR, (outs), (ins GPR:$v, GPR:$b),
!strconcat(instr_asm, " $v, $b"), !strconcat(instr_asm, " $v, $b"),
[(OpNode GPR:$v, GPR:$b)], IIAlu> [(OpNode GPR:$v, GPR:$b)], IIC_FSLp>
{ {
bits<5> ra; bits<5> ra;
bits<5> rb; bits<5> rb;
@ -77,7 +77,7 @@ class FSLPutD<bits<6> op, bits<4> flags, string instr_asm, Intrinsic OpNode> :
class FSLPutT<bits<6> op, bits<4> flags, string instr_asm, Intrinsic OpNode> : class FSLPutT<bits<6> op, bits<4> flags, string instr_asm, Intrinsic OpNode> :
MBlazeInst<op, FCX, (outs), (ins fslimm:$b), MBlazeInst<op, FCX, (outs), (ins fslimm:$b),
!strconcat(instr_asm, " $b"), !strconcat(instr_asm, " $b"),
[(OpNode immZExt4:$b)], IIAlu> [(OpNode immZExt4:$b)], IIC_FSLp>
{ {
bits<4> fslno; bits<4> fslno;
@ -92,7 +92,7 @@ class FSLPutT<bits<6> op, bits<4> flags, string instr_asm, Intrinsic OpNode> :
class FSLPutTD<bits<6> op, bits<4> flags, string instr_asm, Intrinsic OpNode> : class FSLPutTD<bits<6> op, bits<4> flags, string instr_asm, Intrinsic OpNode> :
MBlazeInst<op, FCR, (outs), (ins GPR:$b), MBlazeInst<op, FCR, (outs), (ins GPR:$b),
!strconcat(instr_asm, " $b"), !strconcat(instr_asm, " $b"),
[(OpNode GPR:$b)], IIAlu> [(OpNode GPR:$b)], IIC_FSLp>
{ {
bits<5> rb; bits<5> rb;

2
lib/Target/MBlaze/MBlazeInstrFormats.td
View File

@ -81,7 +81,7 @@ class MBlazeInst<bits<6> op, Format form, dag outs, dag ins, string asmstr,
// Pseudo instruction class // Pseudo instruction class
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class MBlazePseudo<dag outs, dag ins, string asmstr, list<dag> pattern>: class MBlazePseudo<dag outs, dag ins, string asmstr, list<dag> pattern>:
MBlazeInst<0x0, FPseudo, outs, ins, asmstr, pattern, IIPseudo>; MBlazeInst<0x0, FPseudo, outs, ins, asmstr, pattern, IIC_Pseudo>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Type A instruction class in MBlaze : <|opcode|rd|ra|rb|flags|> // Type A instruction class in MBlaze : <|opcode|rd|ra|rb|flags|>

2
lib/Target/MBlaze/MBlazeInstrInfo.cpp
View File

@ -17,6 +17,8 @@
#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
#include "MBlazeGenInstrInfo.inc" #include "MBlazeGenInstrInfo.inc"

1
lib/Target/MBlaze/MBlazeInstrInfo.h
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@ -261,7 +261,6 @@ public:
virtual bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) virtual bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
const; const;
virtual void copyPhysReg(MachineBasicBlock &MBB, virtual void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, DebugLoc DL, MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DestReg, unsigned SrcReg, unsigned DestReg, unsigned SrcReg,

150
lib/Target/MBlaze/MBlazeInstrInfo.td
View File

@ -47,22 +47,22 @@ def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MBCallSeqEnd,
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// MBlaze Instruction Predicate Definitions. // MBlaze Instruction Predicate Definitions.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def HasPipe3 : Predicate<"Subtarget.hasPipe3()">; // def HasPipe3 : Predicate<"Subtarget.hasPipe3()">;
def HasBarrel : Predicate<"Subtarget.hasBarrel()">; def HasBarrel : Predicate<"Subtarget.hasBarrel()">;
def NoBarrel : Predicate<"!Subtarget.hasBarrel()">; // def NoBarrel : Predicate<"!Subtarget.hasBarrel()">;
def HasDiv : Predicate<"Subtarget.hasDiv()">; def HasDiv : Predicate<"Subtarget.hasDiv()">;
def HasMul : Predicate<"Subtarget.hasMul()">; def HasMul : Predicate<"Subtarget.hasMul()">;
def HasFSL : Predicate<"Subtarget.hasFSL()">; // def HasFSL : Predicate<"Subtarget.hasFSL()">;
def HasEFSL : Predicate<"Subtarget.hasEFSL()">; // def HasEFSL : Predicate<"Subtarget.hasEFSL()">;
def HasMSRSet : Predicate<"Subtarget.hasMSRSet()">; // def HasMSRSet : Predicate<"Subtarget.hasMSRSet()">;
def HasException : Predicate<"Subtarget.hasException()">; // def HasException : Predicate<"Subtarget.hasException()">;
def HasPatCmp : Predicate<"Subtarget.hasPatCmp()">; def HasPatCmp : Predicate<"Subtarget.hasPatCmp()">;
def HasFPU : Predicate<"Subtarget.hasFPU()">; def HasFPU : Predicate<"Subtarget.hasFPU()">;
def HasESR : Predicate<"Subtarget.hasESR()">; // def HasESR : Predicate<"Subtarget.hasESR()">;
def HasPVR : Predicate<"Subtarget.hasPVR()">; // def HasPVR : Predicate<"Subtarget.hasPVR()">;
def HasMul64 : Predicate<"Subtarget.hasMul64()">; def HasMul64 : Predicate<"Subtarget.hasMul64()">;
def HasSqrt : Predicate<"Subtarget.hasSqrt()">; def HasSqrt : Predicate<"Subtarget.hasSqrt()">;
def HasMMU : Predicate<"Subtarget.hasMMU()">; // def HasMMU : Predicate<"Subtarget.hasMMU()">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// MBlaze Operand, Complex Patterns and Transformations Definitions. // MBlaze Operand, Complex Patterns and Transformations Definitions.
@ -170,18 +170,18 @@ class ArithI<bits<6> op, string instr_asm, SDNode OpNode,
Operand Od, PatLeaf imm_type> : Operand Od, PatLeaf imm_type> :
TB<op, (outs GPR:$dst), (ins GPR:$b, Od:$c), TB<op, (outs GPR:$dst), (ins GPR:$b, Od:$c),
!strconcat(instr_asm, " $dst, $b, $c"), !strconcat(instr_asm, " $dst, $b, $c"),
[(set GPR:$dst, (OpNode GPR:$b, imm_type:$c))], IIAlu>; [(set GPR:$dst, (OpNode GPR:$b, imm_type:$c))], IIC_ALU>;
class ArithI32<bits<6> op, string instr_asm,Operand Od, PatLeaf imm_type> : class ArithI32<bits<6> op, string instr_asm,Operand Od, PatLeaf imm_type> :
TB<op, (outs GPR:$dst), (ins GPR:$b, Od:$c), TB<op, (outs GPR:$dst), (ins GPR:$b, Od:$c),
!strconcat(instr_asm, " $dst, $b, $c"), !strconcat(instr_asm, " $dst, $b, $c"),
[], IIAlu>; [], IIC_ALU>;
class ShiftI<bits<6> op, bits<2> flags, string instr_asm, SDNode OpNode, class ShiftI<bits<6> op, bits<2> flags, string instr_asm, SDNode OpNode,
Operand Od, PatLeaf imm_type> : Operand Od, PatLeaf imm_type> :
SHT<op, flags, (outs GPR:$dst), (ins GPR:$b, Od:$c), SHT<op, flags, (outs GPR:$dst), (ins GPR:$b, Od:$c),
!strconcat(instr_asm, " $dst, $b, $c"), !strconcat(instr_asm, " $dst, $b, $c"),
[(set GPR:$dst, (OpNode GPR:$b, imm_type:$c))], IIAlu>; [(set GPR:$dst, (OpNode GPR:$b, imm_type:$c))], IIC_SHT>;
class ArithR<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode, class ArithR<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode,
InstrItinClass itin> : InstrItinClass itin> :
@ -193,7 +193,7 @@ class ArithRI<bits<6> op, string instr_asm, SDNode OpNode,
Operand Od, PatLeaf imm_type> : Operand Od, PatLeaf imm_type> :
TBR<op, (outs GPR:$dst), (ins Od:$b, GPR:$c), TBR<op, (outs GPR:$dst), (ins Od:$b, GPR:$c),
!strconcat(instr_asm, " $dst, $c, $b"), !strconcat(instr_asm, " $dst, $c, $b"),
[(set GPR:$dst, (OpNode imm_type:$b, GPR:$c))], IIAlu>; [(set GPR:$dst, (OpNode imm_type:$b, GPR:$c))], IIC_ALU>;
class ArithN<bits<6> op, bits<11> flags, string instr_asm, class ArithN<bits<6> op, bits<11> flags, string instr_asm,
InstrItinClass itin> : InstrItinClass itin> :
@ -204,7 +204,7 @@ class ArithN<bits<6> op, bits<11> flags, string instr_asm,
class ArithNI<bits<6> op, string instr_asm,Operand Od, PatLeaf imm_type> : class ArithNI<bits<6> op, string instr_asm,Operand Od, PatLeaf imm_type> :
TB<op, (outs GPR:$dst), (ins GPR:$b, Od:$c), TB<op, (outs GPR:$dst), (ins GPR:$b, Od:$c),
!strconcat(instr_asm, " $dst, $b, $c"), !strconcat(instr_asm, " $dst, $b, $c"),
[], IIAlu>; [], IIC_ALU>;
class ArithRN<bits<6> op, bits<11> flags, string instr_asm, class ArithRN<bits<6> op, bits<11> flags, string instr_asm,
InstrItinClass itin> : InstrItinClass itin> :
@ -215,7 +215,7 @@ class ArithRN<bits<6> op, bits<11> flags, string instr_asm,
class ArithRNI<bits<6> op, string instr_asm,Operand Od, PatLeaf imm_type> : class ArithRNI<bits<6> op, string instr_asm,Operand Od, PatLeaf imm_type> :
TBR<op, (outs GPR:$dst), (ins Od:$c, GPR:$b), TBR<op, (outs GPR:$dst), (ins Od:$c, GPR:$b),
!strconcat(instr_asm, " $dst, $b, $c"), !strconcat(instr_asm, " $dst, $b, $c"),
[], IIAlu>; [], IIC_ALU>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Misc Arithmetic Instructions // Misc Arithmetic Instructions
@ -224,23 +224,23 @@ class ArithRNI<bits<6> op, string instr_asm,Operand Od, PatLeaf imm_type> :
class Logic<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode> : class Logic<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode> :
TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c), TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
!strconcat(instr_asm, " $dst, $b, $c"), !strconcat(instr_asm, " $dst, $b, $c"),
[(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], IIAlu>; [(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], IIC_ALU>;
class LogicI<bits<6> op, string instr_asm, SDNode OpNode> : class LogicI<bits<6> op, string instr_asm, SDNode OpNode> :
TB<op, (outs GPR:$dst), (ins GPR:$b, uimm16:$c), TB<op, (outs GPR:$dst), (ins GPR:$b, uimm16:$c),
!strconcat(instr_asm, " $dst, $b, $c"), !strconcat(instr_asm, " $dst, $b, $c"),
[(set GPR:$dst, (OpNode GPR:$b, immZExt16:$c))], [(set GPR:$dst, (OpNode GPR:$b, immZExt16:$c))],
IIAlu>; IIC_ALU>;
class LogicI32<bits<6> op, string instr_asm> : class LogicI32<bits<6> op, string instr_asm> :
TB<op, (outs GPR:$dst), (ins GPR:$b, uimm16:$c), TB<op, (outs GPR:$dst), (ins GPR:$b, uimm16:$c),
!strconcat(instr_asm, " $dst, $b, $c"), !strconcat(instr_asm, " $dst, $b, $c"),
[], IIAlu>; [], IIC_ALU>;
class PatCmp<bits<6> op, bits<11> flags, string instr_asm> : class PatCmp<bits<6> op, bits<11> flags, string instr_asm> :
TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c), TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
!strconcat(instr_asm, " $dst, $b, $c"), !strconcat(instr_asm, " $dst, $b, $c"),
[], IIAlu>; [], IIC_ALU>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Memory Access Instructions // Memory Access Instructions
@ -248,22 +248,22 @@ class PatCmp<bits<6> op, bits<11> flags, string instr_asm> :
class LoadM<bits<6> op, bits<11> flags, string instr_asm> : class LoadM<bits<6> op, bits<11> flags, string instr_asm> :
TA<op, flags, (outs GPR:$dst), (ins memrr:$addr), TA<op, flags, (outs GPR:$dst), (ins memrr:$addr),
!strconcat(instr_asm, " $dst, $addr"), !strconcat(instr_asm, " $dst, $addr"),
[], IILoad>; [], IIC_MEMl>;
class LoadMI<bits<6> op, string instr_asm, PatFrag OpNode> : class LoadMI<bits<6> op, string instr_asm, PatFrag OpNode> :
TB<op, (outs GPR:$dst), (ins memri:$addr), TB<op, (outs GPR:$dst), (ins memri:$addr),
!strconcat(instr_asm, " $dst, $addr"), !strconcat(instr_asm, " $dst, $addr"),
[(set (i32 GPR:$dst), (OpNode iaddr:$addr))], IILoad>; [(set (i32 GPR:$dst), (OpNode iaddr:$addr))], IIC_MEMl>;
class StoreM<bits<6> op, bits<11> flags, string instr_asm> : class StoreM<bits<6> op, bits<11> flags, string instr_asm> :
TA<op, flags, (outs), (ins GPR:$dst, memrr:$addr), TA<op, flags, (outs), (ins GPR:$dst, memrr:$addr),
!strconcat(instr_asm, " $dst, $addr"), !strconcat(instr_asm, " $dst, $addr"),
[], IIStore>; [], IIC_MEMs>;
class StoreMI<bits<6> op, string instr_asm, PatFrag OpNode> : class StoreMI<bits<6> op, string instr_asm, PatFrag OpNode> :
TB<op, (outs), (ins GPR:$dst, memri:$addr), TB<op, (outs), (ins GPR:$dst, memri:$addr),
!strconcat(instr_asm, " $dst, $addr"), !strconcat(instr_asm, " $dst, $addr"),
[(OpNode (i32 GPR:$dst), iaddr:$addr)], IIStore>; [(OpNode (i32 GPR:$dst), iaddr:$addr)], IIC_MEMs>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Branch Instructions // Branch Instructions
@ -271,7 +271,7 @@ class StoreMI<bits<6> op, string instr_asm, PatFrag OpNode> :
class Branch<bits<6> op, bits<5> br, bits<11> flags, string instr_asm> : class Branch<bits<6> op, bits<5> br, bits<11> flags, string instr_asm> :
TA<op, flags, (outs), (ins GPR:$target), TA<op, flags, (outs), (ins GPR:$target),
!strconcat(instr_asm, " $target"), !strconcat(instr_asm, " $target"),
[], IIBranch> { [], IIC_BR> {
let rd = 0x0; let rd = 0x0;
let ra = br; let ra = br;
let Form = FCCR; let Form = FCCR;
@ -280,7 +280,7 @@ class Branch<bits<6> op, bits<5> br, bits<11> flags, string instr_asm> :
class BranchI<bits<6> op, bits<5> br, string instr_asm> : class BranchI<bits<6> op, bits<5> br, string instr_asm> :
TB<op, (outs), (ins brtarget:$target), TB<op, (outs), (ins brtarget:$target),
!strconcat(instr_asm, " $target"), !strconcat(instr_asm, " $target"),
[], IIBranch> { [], IIC_BR> {
let rd = 0; let rd = 0;
let ra = br; let ra = br;
let Form = FCCI; let Form = FCCI;
@ -292,7 +292,7 @@ class BranchI<bits<6> op, bits<5> br, string instr_asm> :
class BranchL<bits<6> op, bits<5> br, bits<11> flags, string instr_asm> : class BranchL<bits<6> op, bits<5> br, bits<11> flags, string instr_asm> :
TA<op, flags, (outs), (ins GPR:$link, GPR:$target, variable_ops), TA<op, flags, (outs), (ins GPR:$link, GPR:$target, variable_ops),
!strconcat(instr_asm, " $link, $target"), !strconcat(instr_asm, " $link, $target"),
[], IIBranch> { [], IIC_BRl> {
let ra = br; let ra = br;
let Form = FRCR; let Form = FRCR;
} }
@ -300,7 +300,7 @@ class BranchL<bits<6> op, bits<5> br, bits<11> flags, string instr_asm> :
class BranchLI<bits<6> op, bits<5> br, string instr_asm> : class BranchLI<bits<6> op, bits<5> br, string instr_asm> :
TB<op, (outs), (ins GPR:$link, calltarget:$target, variable_ops), TB<op, (outs), (ins GPR:$link, calltarget:$target, variable_ops),
!strconcat(instr_asm, " $link, $target"), !strconcat(instr_asm, " $link, $target"),
[], IIBranch> { [], IIC_BRl> {
let ra = br; let ra = br;
let Form = FRCI; let Form = FRCI;
} }
@ -312,7 +312,7 @@ class BranchC<bits<6> op, bits<5> br, bits<11> flags, string instr_asm> :
TA<op, flags, (outs), TA<op, flags, (outs),
(ins GPR:$a, GPR:$b), (ins GPR:$a, GPR:$b),
!strconcat(instr_asm, " $a, $b"), !strconcat(instr_asm, " $a, $b"),
[], IIBranch> { [], IIC_BRc> {
let rd = br; let rd = br;
let Form = FCRR; let Form = FCRR;
} }
@ -320,7 +320,7 @@ class BranchC<bits<6> op, bits<5> br, bits<11> flags, string instr_asm> :
class BranchCI<bits<6> op, bits<5> br, string instr_asm> : class BranchCI<bits<6> op, bits<5> br, string instr_asm> :
TB<op, (outs), (ins GPR:$a, brtarget:$offset), TB<op, (outs), (ins GPR:$a, brtarget:$offset),
!strconcat(instr_asm, " $a, $offset"), !strconcat(instr_asm, " $a, $offset"),
[], IIBranch> { [], IIC_BRc> {
let rd = br; let rd = br;
let Form = FCRI; let Form = FCRI;
} }
@ -330,71 +330,74 @@ class BranchCI<bits<6> op, bits<5> br, string instr_asm> :
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let isCommutable = 1, isAsCheapAsAMove = 1 in { let isCommutable = 1, isAsCheapAsAMove = 1 in {
def ADDK : Arith<0x04, 0x000, "addk ", add, IIAlu>; def ADDK : Arith<0x04, 0x000, "addk ", add, IIC_ALU>;
def AND : Logic<0x21, 0x000, "and ", and>; def AND : Logic<0x21, 0x000, "and ", and>;
def OR : Logic<0x20, 0x000, "or ", or>; def OR : Logic<0x20, 0x000, "or ", or>;
def XOR : Logic<0x22, 0x000, "xor ", xor>; def XOR : Logic<0x22, 0x000, "xor ", xor>;
def PCMPBF : PatCmp<0x20, 0x400, "pcmpbf ">;
def PCMPEQ : PatCmp<0x22, 0x400, "pcmpeq ">; let Predicates=[HasPatCmp] in {
def PCMPNE : PatCmp<0x23, 0x400, "pcmpne ">; def PCMPBF : PatCmp<0x20, 0x400, "pcmpbf ">;
def PCMPEQ : PatCmp<0x22, 0x400, "pcmpeq ">;
def PCMPNE : PatCmp<0x23, 0x400, "pcmpne ">;
}
let Defs = [CARRY] in { let Defs = [CARRY] in {
def ADD : Arith<0x00, 0x000, "add ", addc, IIAlu>; def ADD : Arith<0x00, 0x000, "add ", addc, IIC_ALU>;
let Uses = [CARRY] in { let Uses = [CARRY] in {
def ADDC : Arith<0x02, 0x000, "addc ", adde, IIAlu>; def ADDC : Arith<0x02, 0x000, "addc ", adde, IIC_ALU>;
} }
} }
let Uses = [CARRY] in { let Uses = [CARRY] in {
def ADDKC : ArithN<0x06, 0x000, "addkc ", IIAlu>; def ADDKC : ArithN<0x06, 0x000, "addkc ", IIC_ALU>;
} }
} }
let isAsCheapAsAMove = 1 in { let isAsCheapAsAMove = 1 in {
def ANDN : ArithN<0x23, 0x000, "andn ", IIAlu>; def ANDN : ArithN<0x23, 0x000, "andn ", IIC_ALU>;
def CMP : ArithN<0x05, 0x001, "cmp ", IIAlu>; def CMP : ArithN<0x05, 0x001, "cmp ", IIC_ALU>;
def CMPU : ArithN<0x05, 0x003, "cmpu ", IIAlu>; def CMPU : ArithN<0x05, 0x003, "cmpu ", IIC_ALU>;
def RSUBK : ArithR<0x05, 0x000, "rsubk ", sub, IIAlu>; def RSUBK : ArithR<0x05, 0x000, "rsubk ", sub, IIC_ALU>;
let Defs = [CARRY] in { let Defs = [CARRY] in {
def RSUB : ArithR<0x01, 0x000, "rsub ", subc, IIAlu>; def RSUB : ArithR<0x01, 0x000, "rsub ", subc, IIC_ALU>;
let Uses = [CARRY] in { let Uses = [CARRY] in {
def RSUBC : ArithR<0x03, 0x000, "rsubc ", sube, IIAlu>; def RSUBC : ArithR<0x03, 0x000, "rsubc ", sube, IIC_ALU>;
} }
} }
let Uses = [CARRY] in { let Uses = [CARRY] in {
def RSUBKC : ArithRN<0x07, 0x000, "rsubkc ", IIAlu>; def RSUBKC : ArithRN<0x07, 0x000, "rsubkc ", IIC_ALU>;
} }
} }
let isCommutable = 1, Predicates=[HasMul] in { let isCommutable = 1, Predicates=[HasMul] in {
def MUL : Arith<0x10, 0x000, "mul ", mul, IIAlu>; def MUL : Arith<0x10, 0x000, "mul ", mul, IIC_ALUm>;
} }
let isCommutable = 1, Predicates=[HasMul,HasMul64] in { let isCommutable = 1, Predicates=[HasMul,HasMul64] in {
def MULH : Arith<0x10, 0x001, "mulh ", mulhs, IIAlu>; def MULH : Arith<0x10, 0x001, "mulh ", mulhs, IIC_ALUm>;
def MULHU : Arith<0x10, 0x003, "mulhu ", mulhu, IIAlu>; def MULHU : Arith<0x10, 0x003, "mulhu ", mulhu, IIC_ALUm>;
} }
let Predicates=[HasMul,HasMul64] in { let Predicates=[HasMul,HasMul64] in {
def MULHSU : ArithN<0x10, 0x002, "mulhsu ", IIAlu>; def MULHSU : ArithN<0x10, 0x002, "mulhsu ", IIC_ALUm>;
} }
let Predicates=[HasBarrel] in { let Predicates=[HasBarrel] in {
def BSRL : Arith<0x11, 0x000, "bsrl ", srl, IIAlu>; def BSRL : Arith<0x11, 0x000, "bsrl ", srl, IIC_SHT>;
def BSRA : Arith<0x11, 0x200, "bsra ", sra, IIAlu>; def BSRA : Arith<0x11, 0x200, "bsra ", sra, IIC_SHT>;
def BSLL : Arith<0x11, 0x400, "bsll ", shl, IIAlu>; def BSLL : Arith<0x11, 0x400, "bsll ", shl, IIC_SHT>;
def BSRLI : ShiftI<0x19, 0x0, "bsrli ", srl, uimm5, immZExt5>; def BSRLI : ShiftI<0x19, 0x0, "bsrli ", srl, uimm5, immZExt5>;
def BSRAI : ShiftI<0x19, 0x1, "bsrai ", sra, uimm5, immZExt5>; def BSRAI : ShiftI<0x19, 0x1, "bsrai ", sra, uimm5, immZExt5>;
def BSLLI : ShiftI<0x19, 0x2, "bslli ", shl, uimm5, immZExt5>; def BSLLI : ShiftI<0x19, 0x2, "bslli ", shl, uimm5, immZExt5>;
} }
let Predicates=[HasDiv] in { let Predicates=[HasDiv] in {
def IDIV : ArithR<0x12, 0x000, "idiv ", sdiv, IIAlu>; def IDIV : ArithR<0x12, 0x000, "idiv ", sdiv, IIC_ALUd>;
def IDIVU : ArithR<0x12, 0x002, "idivu ", udiv, IIAlu>; def IDIVU : ArithR<0x12, 0x002, "idivu ", udiv, IIC_ALUd>;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@ -552,7 +555,7 @@ let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
def RTSD : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm), def RTSD : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm),
"rtsd $target, $imm", "rtsd $target, $imm",
[], [],
IIBranch>; IIC_BR>;
} }
let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
@ -560,7 +563,7 @@ let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
def RTID : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm), def RTID : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm),
"rtid $target, $imm", "rtid $target, $imm",
[], [],
IIBranch>; IIC_BR>;
} }
let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
@ -568,7 +571,7 @@ let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
def RTBD : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm), def RTBD : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm),
"rtbd $target, $imm", "rtbd $target, $imm",
[], [],
IIBranch>; IIC_BR>;
} }
let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
@ -576,7 +579,7 @@ let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
def RTED : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm), def RTED : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm),
"rted $target, $imm", "rted $target, $imm",
[], [],
IIBranch>; IIC_BR>;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@ -584,7 +587,7 @@ let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let neverHasSideEffects = 1 in { let neverHasSideEffects = 1 in {
def NOP : MBlazeInst< 0x20, FC, (outs), (ins), "nop ", [], IIAlu>; def NOP : MBlazeInst< 0x20, FC, (outs), (ins), "nop ", [], IIC_ALU>;
} }
let usesCustomInserter = 1 in { let usesCustomInserter = 1 in {
@ -611,17 +614,17 @@ let usesCustomInserter = 1 in {
let rb = 0 in { let rb = 0 in {
def SEXT16 : TA<0x24, 0x061, (outs GPR:$dst), (ins GPR:$src), def SEXT16 : TA<0x24, 0x061, (outs GPR:$dst), (ins GPR:$src),
"sext16 $dst, $src", [], IIAlu>; "sext16 $dst, $src", [], IIC_ALU>;
def SEXT8 : TA<0x24, 0x060, (outs GPR:$dst), (ins GPR:$src), def SEXT8 : TA<0x24, 0x060, (outs GPR:$dst), (ins GPR:$src),
"sext8 $dst, $src", [], IIAlu>; "sext8 $dst, $src", [], IIC_ALU>;
let Defs = [CARRY] in { let Defs = [CARRY] in {
def SRL : TA<0x24, 0x041, (outs GPR:$dst), (ins GPR:$src), def SRL : TA<0x24, 0x041, (outs GPR:$dst), (ins GPR:$src),
"srl $dst, $src", [], IIAlu>; "srl $dst, $src", [], IIC_ALU>;
def SRA : TA<0x24, 0x001, (outs GPR:$dst), (ins GPR:$src), def SRA : TA<0x24, 0x001, (outs GPR:$dst), (ins GPR:$src),
"sra $dst, $src", [], IIAlu>; "sra $dst, $src", [], IIC_ALU>;
let Uses = [CARRY] in { let Uses = [CARRY] in {
def SRC : TA<0x24, 0x021, (outs GPR:$dst), (ins GPR:$src), def SRC : TA<0x24, 0x021, (outs GPR:$dst), (ins GPR:$src),
"src $dst, $src", [], IIAlu>; "src $dst, $src", [], IIC_ALU>;
} }
} }
} }
@ -637,36 +640,36 @@ let isCodeGenOnly=1 in {
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let Form=FRCS in { let Form=FRCS in {
def MFS : SPC<0x25, 0x2, (outs GPR:$dst), (ins SPR:$src), def MFS : SPC<0x25, 0x2, (outs GPR:$dst), (ins SPR:$src),
"mfs $dst, $src", [], IIAlu>; "mfs $dst, $src", [], IIC_ALU>;
} }
let Form=FCRCS in { let Form=FCRCS in {
def MTS : SPC<0x25, 0x3, (outs SPR:$dst), (ins GPR:$src), def MTS : SPC<0x25, 0x3, (outs SPR:$dst), (ins GPR:$src),
"mts $dst, $src", [], IIAlu>; "mts $dst, $src", [], IIC_ALU>;
} }
def MSRSET : MSR<0x25, 0x20, (outs GPR:$dst), (ins uimm15:$set), def MSRSET : MSR<0x25, 0x20, (outs GPR:$dst), (ins uimm15:$set),
"msrset $dst, $set", [], IIAlu>; "msrset $dst, $set", [], IIC_ALU>;
def MSRCLR : MSR<0x25, 0x22, (outs GPR:$dst), (ins uimm15:$clr), def MSRCLR : MSR<0x25, 0x22, (outs GPR:$dst), (ins uimm15:$clr),
"msrclr $dst, $clr", [], IIAlu>; "msrclr $dst, $clr", [], IIC_ALU>;
let rd=0x0, Form=FCRR in { let rd=0x0, Form=FCRR in {
def WDC : TA<0x24, 0x64, (outs), (ins GPR:$a, GPR:$b), def WDC : TA<0x24, 0x64, (outs), (ins GPR:$a, GPR:$b),
"wdc $a, $b", [], IIAlu>; "wdc $a, $b", [], IIC_WDC>;
def WDCF : TA<0x24, 0x74, (outs), (ins GPR:$a, GPR:$b), def WDCF : TA<0x24, 0x74, (outs), (ins GPR:$a, GPR:$b),
"wdc.flush $a, $b", [], IIAlu>; "wdc.flush $a, $b", [], IIC_WDC>;
def WDCC : TA<0x24, 0x66, (outs), (ins GPR:$a, GPR:$b), def WDCC : TA<0x24, 0x66, (outs), (ins GPR:$a, GPR:$b),
"wdc.clear $a, $b", [], IIAlu>; "wdc.clear $a, $b", [], IIC_WDC>;
def WIC : TA<0x24, 0x68, (outs), (ins GPR:$a, GPR:$b), def WIC : TA<0x24, 0x68, (outs), (ins GPR:$a, GPR:$b),
"wic $a, $b", [], IIAlu>; "wic $a, $b", [], IIC_WDC>;
} }
def BRK : BranchL<0x26, 0x0C, 0x000, "brk ">; def BRK : BranchL<0x26, 0x0C, 0x000, "brk ">;
def BRKI : BranchLI<0x2E, 0x0C, "brki ">; def BRKI : BranchLI<0x2E, 0x0C, "brki ">;
def IMM : MBlazeInst<0x2C, FCCI, (outs), (ins simm16:$imm), def IMM : MBlazeInst<0x2C, FCCI, (outs), (ins simm16:$imm),
"imm $imm", [], IIAlu>; "imm $imm", [], IIC_ALU>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Pseudo instructions for atomic operations // Pseudo instructions for atomic operations
@ -848,11 +851,6 @@ def : Pat<(MBWrapper tconstpool:$in), (ORI (i32 R0), tconstpool:$in)>;
// Misc instructions // Misc instructions
def : Pat<(and (i32 GPR:$lh), (not (i32 GPR:$rh))),(ANDN GPR:$lh, GPR:$rh)>; def : Pat<(and (i32 GPR:$lh), (not (i32 GPR:$rh))),(ANDN GPR:$lh, GPR:$rh)>;
// Arithmetic with immediates
def : Pat<(add (i32 GPR:$in), imm:$imm),(ADDIK GPR:$in, imm:$imm)>;
def : Pat<(or (i32 GPR:$in), imm:$imm),(ORI GPR:$in, imm:$imm)>;
def : Pat<(xor (i32 GPR:$in), imm:$imm),(XORI GPR:$in, imm:$imm)>;
// Convert any extend loads into zero extend loads // Convert any extend loads into zero extend loads
def : Pat<(extloadi8 iaddr:$src), (i32 (LBUI iaddr:$src))>; def : Pat<(extloadi8 iaddr:$src), (i32 (LBUI iaddr:$src))>;
def : Pat<(extloadi16 iaddr:$src), (i32 (LHUI iaddr:$src))>; def : Pat<(extloadi16 iaddr:$src), (i32 (LHUI iaddr:$src))>;

25
lib/Target/MBlaze/MBlazeRegisterInfo.td
View File

@ -85,18 +85,19 @@ let Namespace = "MBlaze" in {
def RTLBX : MBlazeSPRReg<0x1002, "rtlbx">, DwarfRegNum<[41]>; def RTLBX : MBlazeSPRReg<0x1002, "rtlbx">, DwarfRegNum<[41]>;
def RTLBLO : MBlazeSPRReg<0x1003, "rtlblo">, DwarfRegNum<[42]>; def RTLBLO : MBlazeSPRReg<0x1003, "rtlblo">, DwarfRegNum<[42]>;
def RTLBHI : MBlazeSPRReg<0x1004, "rtlbhi">, DwarfRegNum<[43]>; def RTLBHI : MBlazeSPRReg<0x1004, "rtlbhi">, DwarfRegNum<[43]>;
def RPVR0 : MBlazeSPRReg<0x2000, "rpvr0">, DwarfRegNum<[44]>; def RTLBSX : MBlazeSPRReg<0x1004, "rtlbsx">, DwarfRegNum<[44]>;
def RPVR1 : MBlazeSPRReg<0x2001, "rpvr1">, DwarfRegNum<[45]>; def RPVR0 : MBlazeSPRReg<0x2000, "rpvr0">, DwarfRegNum<[45]>;
def RPVR2 : MBlazeSPRReg<0x2002, "rpvr2">, DwarfRegNum<[46]>; def RPVR1 : MBlazeSPRReg<0x2001, "rpvr1">, DwarfRegNum<[46]>;
def RPVR3 : MBlazeSPRReg<0x2003, "rpvr3">, DwarfRegNum<[47]>; def RPVR2 : MBlazeSPRReg<0x2002, "rpvr2">, DwarfRegNum<[47]>;
def RPVR4 : MBlazeSPRReg<0x2004, "rpvr4">, DwarfRegNum<[48]>; def RPVR3 : MBlazeSPRReg<0x2003, "rpvr3">, DwarfRegNum<[48]>;
def RPVR5 : MBlazeSPRReg<0x2005, "rpvr5">, DwarfRegNum<[49]>; def RPVR4 : MBlazeSPRReg<0x2004, "rpvr4">, DwarfRegNum<[49]>;
def RPVR6 : MBlazeSPRReg<0x2006, "rpvr6">, DwarfRegNum<[50]>; def RPVR5 : MBlazeSPRReg<0x2005, "rpvr5">, DwarfRegNum<[50]>;
def RPVR7 : MBlazeSPRReg<0x2007, "rpvr7">, DwarfRegNum<[51]>; def RPVR6 : MBlazeSPRReg<0x2006, "rpvr6">, DwarfRegNum<[51]>;
def RPVR8 : MBlazeSPRReg<0x2008, "rpvr8">, DwarfRegNum<[52]>; def RPVR7 : MBlazeSPRReg<0x2007, "rpvr7">, DwarfRegNum<[52]>;
def RPVR9 : MBlazeSPRReg<0x2009, "rpvr9">, DwarfRegNum<[53]>; def RPVR8 : MBlazeSPRReg<0x2008, "rpvr8">, DwarfRegNum<[53]>;
def RPVR10 : MBlazeSPRReg<0x200A, "rpvr10">, DwarfRegNum<[54]>; def RPVR9 : MBlazeSPRReg<0x2009, "rpvr9">, DwarfRegNum<[54]>;
def RPVR11 : MBlazeSPRReg<0x200B, "rpvr11">, DwarfRegNum<[55]>; def RPVR10 : MBlazeSPRReg<0x200A, "rpvr10">, DwarfRegNum<[55]>;
def RPVR11 : MBlazeSPRReg<0x200B, "rpvr11">, DwarfRegNum<[56]>;
// The carry bit. In the Microblaze this is really bit 29 of the // The carry bit. In the Microblaze this is really bit 29 of the
// MSR register but this is the only bit of that register that we // MSR register but this is the only bit of that register that we

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//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Functional units across MBlaze chips sets. Based on GCC/MBlaze backend files. // MBlaze functional units.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def ALU : FuncUnit; def IF : FuncUnit;
def IMULDIV : FuncUnit; def ID : FuncUnit;
def EX : FuncUnit;
def MA : FuncUnit;
def WB : FuncUnit;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Instruction Itinerary classes used for MBlaze // Instruction Itinerary classes used for MBlaze
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def IIAlu : InstrItinClass; def IIC_ALU : InstrItinClass;
def IILoad : InstrItinClass; def IIC_ALUm : InstrItinClass;
def IIStore : InstrItinClass; def IIC_ALUd : InstrItinClass;
def IIXfer : InstrItinClass; def IIC_SHT : InstrItinClass;
def IIBranch : InstrItinClass; def IIC_FSLg : InstrItinClass;
def IIHiLo : InstrItinClass; def IIC_FSLp : InstrItinClass;
def IIImul : InstrItinClass; def IIC_MEMs : InstrItinClass;
def IIIdiv : InstrItinClass; def IIC_MEMl : InstrItinClass;
def IIFcvt : InstrItinClass; def IIC_FPU : InstrItinClass;
def IIFmove : InstrItinClass; def IIC_FPUd : InstrItinClass;
def IIFcmp : InstrItinClass; def IIC_FPUf : InstrItinClass;
def IIFadd : InstrItinClass; def IIC_FPUi : InstrItinClass;
def IIFmulSingle : InstrItinClass; def IIC_FPUs : InstrItinClass;
def IIFmulDouble : InstrItinClass; def IIC_FPUc : InstrItinClass;
def IIFdivSingle : InstrItinClass; def IIC_BR : InstrItinClass;
def IIFdivDouble : InstrItinClass; def IIC_BRc : InstrItinClass;
def IIFsqrtSingle : InstrItinClass; def IIC_BRl : InstrItinClass;
def IIFsqrtDouble : InstrItinClass; def IIC_WDC : InstrItinClass;
def IIFrecipFsqrtStep : InstrItinClass; def IIC_Pseudo : InstrItinClass;
def IIPseudo : InstrItinClass;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// MBlaze Generic instruction itineraries. // MBlaze generic instruction itineraries.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def MBlazeGenericItineraries : ProcessorItineraries< def MBlazeGenericItineraries : ProcessorItineraries<[], [], []>;
[ALU, IMULDIV], [], [
InstrItinData<IIAlu , [InstrStage<1, [ALU]>]>, //===----------------------------------------------------------------------===//
InstrItinData<IILoad , [InstrStage<3, [ALU]>]>, // MBlaze instruction itineraries for three stage pipeline.
InstrItinData<IIStore , [InstrStage<1, [ALU]>]>, //===----------------------------------------------------------------------===//
InstrItinData<IIXfer , [InstrStage<2, [ALU]>]>, include "MBlazeSchedule3.td"
InstrItinData<IIBranch , [InstrStage<1, [ALU]>]>,
InstrItinData<IIHiLo , [InstrStage<1, [IMULDIV]>]>, //===----------------------------------------------------------------------===//
InstrItinData<IIImul , [InstrStage<17, [IMULDIV]>]>, // MBlaze instruction itineraries for five stage pipeline.
InstrItinData<IIIdiv , [InstrStage<38, [IMULDIV]>]>, //===----------------------------------------------------------------------===//
InstrItinData<IIFcvt , [InstrStage<1, [ALU]>]>, include "MBlazeSchedule5.td"
InstrItinData<IIFmove , [InstrStage<2, [ALU]>]>,
InstrItinData<IIFcmp , [InstrStage<3, [ALU]>]>,
InstrItinData<IIFadd , [InstrStage<4, [ALU]>]>,
InstrItinData<IIFmulSingle , [InstrStage<7, [ALU]>]>,
InstrItinData<IIFmulDouble , [InstrStage<8, [ALU]>]>,
InstrItinData<IIFdivSingle , [InstrStage<23, [ALU]>]>,
InstrItinData<IIFdivDouble , [InstrStage<36, [ALU]>]>,
InstrItinData<IIFsqrtSingle , [InstrStage<54, [ALU]>]>,
InstrItinData<IIFsqrtDouble , [InstrStage<12, [ALU]>]>,
InstrItinData<IIFrecipFsqrtStep , [InstrStage<5, [ALU]>]>
]>;

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//===- MBlazeSchedule3.td - MBlaze Scheduling Definitions --*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// MBlaze instruction itineraries for the threee stage pipeline.
//===----------------------------------------------------------------------===//
def MBlazePipe3Itineraries : ProcessorItineraries<
[IF,ID,EX], [], [
// ALU instruction with one destination register and either two register
// source operands or one register source operand and one immediate operand.
// The instruction takes one cycle to execute in each of the stages. The
// two source operands are read during the decode stage and the result is
// ready after the execute stage.
InstrItinData< IIC_ALU,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<1,[EX]>], // one cycle in execute stage
[ 2 // result ready after two cycles
, 1 // first operand read after one cycle
, 1 ]>, // second operand read after one cycle
// ALU multiply instruction with one destination register and either two
// register source operands or one register source operand and one immediate
// operand. The instruction takes one cycle to execute in each of the
// pipeline stages except the execute stage, which takes three cycles. The
// two source operands are read during the decode stage and the result is
// ready after the execute stage.
InstrItinData< IIC_ALUm,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<3,[EX]>], // three cycles in execute stage
[ 4 // result ready after four cycles
, 1 // first operand read after one cycle
, 1 ]>, // second operand read after one cycle
// ALU divide instruction with one destination register two register source
// operands. The instruction takes one cycle to execute in each the pipeline
// stages except the execute stage, which takes 34 cycles. The two
// source operands are read during the decode stage and the result is ready
// after the execute stage.
InstrItinData< IIC_ALUd,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<34,[EX]>], // 34 cycles in execute stage
[ 35 // result ready after 35 cycles
, 1 // first operand read after one cycle
, 1 ]>, // second operand read after one cycle
// Shift instruction with one destination register and either two register
// source operands or one register source operand and one immediate operand.
// The instruction takes one cycle to execute in each of the pipeline stages
// except the execute stage, which takes two cycles. The two source operands
// are read during the decode stage and the result is ready after the execute
// stage.
InstrItinData< IIC_SHT,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<2,[EX]>], // two cycles in execute stage
[ 3 // result ready after three cycles
, 1 // first operand read after one cycle
, 1 ]>, // second operand read after one cycle
// Branch instruction with one source operand register. The instruction takes
// one cycle to execute in each of the pipeline stages. The source operand is
// read during the decode stage.
InstrItinData< IIC_BR,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<1,[EX]>], // one cycle in execute stage
[ 1 ]>, // first operand read after one cycle
// Conditional branch instruction with two source operand registers. The
// instruction takes one cycle to execute in each of the pipeline stages. The
// two source operands are read during the decode stage.
InstrItinData< IIC_BRc,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<1,[EX]>], // one cycle in execute stage
[ 1 // first operand read after one cycle
, 1 ]>, // second operand read after one cycle
// Branch and link instruction with one destination register and one source
// operand register. The instruction takes one cycle to execute in each of
// the pipeline stages. The source operand is read during the decode stage
// and the destination register is ready after the execute stage.
InstrItinData< IIC_BRl,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<1,[EX]>], // one cycle in execute stage
[ 2 // result ready after two cycles
, 1 ]>, // first operand read after one cycle
// Cache control instruction with two source operand registers. The
// instruction takes one cycle to execute in each of the pipeline stages
// except the memory access stage, which takes two cycles. The source
// operands are read during the decode stage.
InstrItinData< IIC_WDC,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<2,[EX]>], // two cycles in execute stage
[ 1 // first operand read after one cycle
, 1 ]>, // second operand read after one cycle
// Floating point instruction with one destination register and two source
// operand registers. The instruction takes one cycle to execute in each of
// the pipeline stages except the execute stage, which takes six cycles. The
// source operands are read during the decode stage and the results are ready
// after the execute stage.
InstrItinData< IIC_FPU,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<6,[EX]>], // six cycles in execute stage
[ 7 // result ready after seven cycles
, 1 // first operand read after one cycle
, 1 ]>, // second operand read after one cycle
// Floating point divide instruction with one destination register and two
// source operand registers. The instruction takes one cycle to execute in
// each of the pipeline stages except the execute stage, which takes 30
// cycles. The source operands are read during the decode stage and the
// results are ready after the execute stage.
InstrItinData< IIC_FPUd,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<30,[EX]>], // one cycle in execute stage
[ 31 // result ready after 31 cycles
, 1 // first operand read after one cycle
, 1 ]>, // second operand read after one cycle
// Convert floating point to integer instruction with one destination
// register and one source operand register. The instruction takes one cycle
// to execute in each of the pipeline stages except the execute stage,
// which takes seven cycles. The source operands are read during the decode
// stage and the results are ready after the execute stage.
InstrItinData< IIC_FPUi,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<7,[EX]>], // seven cycles in execute stage
[ 8 // result ready after eight cycles
, 1 ]>, // first operand read after one cycle
// Convert integer to floating point instruction with one destination
// register and one source operand register. The instruction takes one cycle
// to execute in each of the pipeline stages except the execute stage,
// which takes six cycles. The source operands are read during the decode
// stage and the results are ready after the execute stage.
InstrItinData< IIC_FPUf,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<6,[EX]>], // six cycles in execute stage
[ 7 // result ready after seven cycles
, 1 ]>, // first operand read after one cycle
// Floating point square root instruction with one destination register and
// one source operand register. The instruction takes one cycle to execute in
// each of the pipeline stages except the execute stage, which takes 29
// cycles. The source operands are read during the decode stage and the
// results are ready after the execute stage.
InstrItinData< IIC_FPUs,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<29,[EX]>], // 29 cycles in execute stage
[ 30 // result ready after 30 cycles
, 1 ]>, // first operand read after one cycle
// Floating point comparison instruction with one destination register and
// two source operand registers. The instruction takes one cycle to execute
// in each of the pipeline stages except the execute stage, which takes three
// cycles. The source operands are read during the decode stage and the
// results are ready after the execute stage.
InstrItinData< IIC_FPUc,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<3,[EX]>], // three cycles in execute stage
[ 4 // result ready after four cycles
, 1 // first operand read after one cycle
, 1 ]>, // second operand read after one cycle
// FSL get instruction with one register or immediate source operand and one
// destination register. The instruction takes one cycle to execute in each
// of the pipeline stages except the execute stage, which takes two cycles.
// The one source operand is read during the decode stage and the result is
// ready after the execute stage.
InstrItinData< IIC_FSLg,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<2,[EX]>], // two cycles in execute stage
[ 3 // result ready after two cycles
, 1 ]>, // first operand read after one cycle
// FSL put instruction with either two register source operands or one
// register source operand and one immediate operand. There is no result
// produced by the instruction. The instruction takes one cycle to execute in
// each of the pipeline stages except the execute stage, which takes two
// cycles. The two source operands are read during the decode stage.
InstrItinData< IIC_FSLp,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<2,[EX]>], // two cycles in execute stage
[ 1 // first operand read after one cycle
, 1 ]>, // second operand read after one cycle
// Memory store instruction with either three register source operands or two
// register source operands and one immediate operand. There is no result
// produced by the instruction. The instruction takes one cycle to execute in
// each of the pipeline stages except the execute stage, which takes two
// cycles. All of the source operands are read during the decode stage.
InstrItinData< IIC_MEMs,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<2,[EX]>], // two cycles in execute stage
[ 1 // first operand read after one cycle
, 1 // second operand read after one cycle
, 1 ]>, // third operand read after one cycle
// Memory load instruction with one destination register and either two
// register source operands or one register source operand and one immediate
// operand. The instruction takes one cycle to execute in each of the
// pipeline stages except the execute stage, which takes two cycles. All of
// the source operands are read during the decode stage and the result is
// ready after the execute stage.
InstrItinData< IIC_MEMl,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<2,[EX]>], // two cycles in execute stage
[ 3 // result ready after four cycles
, 1 // second operand read after one cycle
, 1 ]> // third operand read after one cycle
]>;

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//===- MBlazeSchedule5.td - MBlaze Scheduling Definitions --*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// MBlaze instruction itineraries for the five stage pipeline.
//===----------------------------------------------------------------------===//
def MBlazePipe5Itineraries : ProcessorItineraries<
[IF,ID,EX,MA,WB], [], [
// ALU instruction with one destination register and either two register
// source operands or one register source operand and one immediate operand.
// The instruction takes one cycle to execute in each of the stages. The
// two source operands are read during the decode stage and the result is
// ready after the execute stage.
InstrItinData< IIC_ALU,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<1,[EX]> // one cycle in execute stage
, InstrStage<1,[MA]> // one cycle in memory access stage
, InstrStage<1,[WB]>], // one cycle in write back stage
[ 2 // result ready after two cycles
, 1 // first operand read after one cycle
, 1 ]>, // second operand read after one cycle
// ALU multiply instruction with one destination register and either two
// register source operands or one register source operand and one immediate
// operand. The instruction takes one cycle to execute in each of the
// pipeline stages. The two source operands are read during the decode stage
// and the result is ready after the execute stage.
InstrItinData< IIC_ALUm,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<1,[EX]> // one cycle in execute stage
, InstrStage<1,[MA]> // one cycle in memory access stage
, InstrStage<1,[WB]>], // one cycle in write back stage
[ 2 // result ready after two cycles
, 1 // first operand read after one cycle
, 1 ]>, // second operand read after one cycle
// ALU divide instruction with one destination register two register source
// operands. The instruction takes one cycle to execute in each the pipeline
// stages except the memory access stage, which takes 31 cycles. The two
// source operands are read during the decode stage and the result is ready
// after the memory access stage.
InstrItinData< IIC_ALUd,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<1,[EX]> // one cycle in execute stage
, InstrStage<31,[MA]> // 31 cycles in memory access stage
, InstrStage<1,[WB]>], // one cycle in write back stage
[ 33 // result ready after 33 cycles
, 1 // first operand read after one cycle
, 1 ]>, // second operand read after one cycle
// Shift instruction with one destination register and either two register
// source operands or one register source operand and one immediate operand.
// The instruction takes one cycle to execute in each of the pipeline stages.
// The two source operands are read during the decode stage and the result is
// ready after the memory access stage.
InstrItinData< IIC_SHT,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<1,[EX]> // one cycle in execute stage
, InstrStage<1,[MA]> // one cycle in memory access stage
, InstrStage<1,[WB]>], // one cycle in write back stage
[ 3 // result ready after three cycles
, 1 // first operand read after one cycle
, 1 ]>, // second operand read after one cycle
// Branch instruction with one source operand register. The instruction takes
// one cycle to execute in each of the pipeline stages. The source operand is
// read during the decode stage.
InstrItinData< IIC_BR,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<1,[EX]> // one cycle in execute stage
, InstrStage<1,[MA]> // one cycle in memory access stage
, InstrStage<1,[WB]>], // one cycle in write back stage
[ 1 ]>, // first operand read after one cycle
// Conditional branch instruction with two source operand registers. The
// instruction takes one cycle to execute in each of the pipeline stages. The
// two source operands are read during the decode stage.
InstrItinData< IIC_BRc,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<1,[EX]> // one cycle in execute stage
, InstrStage<1,[MA]> // one cycle in memory access stage
, InstrStage<1,[WB]>], // one cycle in write back stage
[ 1 // first operand read after one cycle
, 1 ]>, // second operand read after one cycle
// Branch and link instruction with one destination register and one source
// operand register. The instruction takes one cycle to execute in each of
// the pipeline stages. The source operand is read during the decode stage
// and the destination register is ready after the writeback stage.
InstrItinData< IIC_BRl,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<1,[EX]> // one cycle in execute stage
, InstrStage<1,[MA]> // one cycle in memory access stage
, InstrStage<1,[WB]>], // one cycle in write back stage
[ 4 // result ready after four cycles
, 1 ]>, // first operand read after one cycle
// Cache control instruction with two source operand registers. The
// instruction takes one cycle to execute in each of the pipeline stages
// except the memory access stage, which takes two cycles. The source
// operands are read during the decode stage.
InstrItinData< IIC_WDC,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<1,[EX]> // one cycle in execute stage
, InstrStage<2,[MA]> // two cycles in memory access stage
, InstrStage<1,[WB]>], // one cycle in write back stage
[ 1 // first operand read after one cycle
, 1 ]>, // second operand read after one cycle
// Floating point instruction with one destination register and two source
// operand registers. The instruction takes one cycle to execute in each of
// the pipeline stages except the memory access stage, which takes two
// cycles. The source operands are read during the decode stage and the
// results are ready after the writeback stage.
InstrItinData< IIC_FPU,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<1,[EX]> // one cycle in execute stage
, InstrStage<2,[MA]> // two cycles in memory access stage
, InstrStage<1,[WB]>], // one cycle in write back stage
[ 5 // result ready after five cycles
, 1 // first operand read after one cycle
, 1 ]>, // second operand read after one cycle
// Floating point divide instruction with one destination register and two
// source operand registers. The instruction takes one cycle to execute in
// each of the pipeline stages except the memory access stage, which takes 26
// cycles. The source operands are read during the decode stage and the
// results are ready after the writeback stage.
InstrItinData< IIC_FPUd,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<1,[EX]> // one cycle in execute stage
, InstrStage<26,[MA]> // 26 cycles in memory access stage
, InstrStage<1,[WB]>], // one cycle in write back stage
[ 29 // result ready after 29 cycles
, 1 // first operand read after one cycle
, 1 ]>, // second operand read after one cycle
// Convert floating point to integer instruction with one destination
// register and one source operand register. The instruction takes one cycle
// to execute in each of the pipeline stages except the memory access stage,
// which takes three cycles. The source operands are read during the decode
// stage and the results are ready after the writeback stage.
InstrItinData< IIC_FPUi,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<1,[EX]> // one cycle in execute stage
, InstrStage<3,[MA]> // three cycles in memory access stage
, InstrStage<1,[WB]>], // one cycle in write back stage
[ 6 // result ready after six cycles
, 1 ]>, // first operand read after one cycle
// Convert integer to floating point instruction with one destination
// register and one source operand register. The instruction takes one cycle
// to execute in each of the pipeline stages except the memory access stage,
// which takes two cycles. The source operands are read during the decode
// stage and the results are ready after the writeback stage.
InstrItinData< IIC_FPUf,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<1,[EX]> // one cycle in execute stage
, InstrStage<2,[MA]> // two cycles in memory access stage
, InstrStage<1,[WB]>], // one cycle in write back stage
[ 5 // result ready after five cycles
, 1 ]>, // first operand read after one cycle
// Floating point square root instruction with one destination register and
// one source operand register. The instruction takes one cycle to execute in
// each of the pipeline stages except the memory access stage, which takes 25
// cycles. The source operands are read during the decode stage and the
// results are ready after the writeback stage.
InstrItinData< IIC_FPUs,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<1,[EX]> // one cycle in execute stage
, InstrStage<25,[MA]> // 25 cycles in memory access stage
, InstrStage<1,[WB]>], // one cycle in write back stage
[ 28 // result ready after 28 cycles
, 1 ]>, // first operand read after one cycle
// Floating point comparison instruction with one destination register and
// two source operand registers. The instruction takes one cycle to execute
// in each of the pipeline stages. The source operands are read during the
// decode stage and the results are ready after the execute stage.
InstrItinData< IIC_FPUc,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<1,[EX]> // one cycle in execute stage
, InstrStage<1,[MA]> // one cycle in memory access stage
, InstrStage<1,[WB]>], // one cycle in write back stage
[ 2 // result ready after two cycles
, 1 // first operand read after one cycle
, 1 ]>, // second operand read after one cycle
// FSL get instruction with one register or immediate source operand and one
// destination register. The instruction takes one cycle to execute in each
// of the pipeline stages. The one source operand is read during the decode
// stage and the result is ready after the execute stage.
InstrItinData< IIC_FSLg,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<1,[EX]> // one cycle in execute stage
, InstrStage<1,[MA]> // one cycle in memory access stage
, InstrStage<1,[WB]>], // one cycle in write back stage
[ 2 // result ready after two cycles
, 1 ]>, // first operand read after one cycle
// FSL put instruction with either two register source operands or one
// register source operand and one immediate operand. There is no result
// produced by the instruction. The instruction takes one cycle to execute in
// each of the pipeline stages. The two source operands are read during the
// decode stage.
InstrItinData< IIC_FSLp,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<1,[EX]> // one cycle in execute stage
, InstrStage<1,[MA]> // one cycle in memory access stage
, InstrStage<1,[WB]>], // one cycle in write back stage
[ 1 // first operand read after one cycle
, 1 ]>, // second operand read after one cycle
// Memory store instruction with either three register source operands or two
// register source operands and one immediate operand. There is no result
// produced by the instruction. The instruction takes one cycle to execute in
// each of the pipeline stages. All of the source operands are read during
// the decode stage.
InstrItinData< IIC_MEMs,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<1,[EX]> // one cycle in execute stage
, InstrStage<1,[MA]> // one cycle in memory access stage
, InstrStage<1,[WB]>], // one cycle in write back stage
[ 1 // first operand read after one cycle
, 1 // second operand read after one cycle
, 1 ]>, // third operand read after one cycle
// Memory load instruction with one destination register and either two
// register source operands or one register source operand and one immediate
// operand. The instruction takes one cycle to execute in each of the
// pipeline stages. All of the source operands are read during the decode
// stage and the result is ready after the writeback stage.
InstrItinData< IIC_MEMl,
[ InstrStage<1,[IF]> // one cycle in fetch stage
, InstrStage<1,[ID]> // one cycle in decode stage
, InstrStage<1,[EX]> // one cycle in execute stage
, InstrStage<1,[MA]> // one cycle in memory access stage
, InstrStage<1,[WB]>], // one cycle in write back stage
[ 4 // result ready after four cycles
, 1 // second operand read after one cycle
, 1 ]> // third operand read after one cycle
]>;

36
lib/Target/MBlaze/MBlazeSubtarget.cpp
View File

@ -13,19 +13,39 @@
#include "MBlazeSubtarget.h" #include "MBlazeSubtarget.h"
#include "MBlaze.h" #include "MBlaze.h"
#include "MBlazeRegisterInfo.h"
#include "MBlazeGenSubtarget.inc" #include "MBlazeGenSubtarget.inc"
#include "llvm/Support/CommandLine.h" #include "llvm/Support/CommandLine.h"
using namespace llvm; using namespace llvm;
MBlazeSubtarget::MBlazeSubtarget(const std::string &TT, const std::string &FS): MBlazeSubtarget::MBlazeSubtarget(const std::string &TT, const std::string &FS):
HasPipe3(false), HasBarrel(false), HasDiv(false), HasMul(false), HasBarrel(false), HasDiv(false), HasMul(false), HasPatCmp(false),
HasFSL(false), HasEFSL(false), HasMSRSet(false), HasException(false), HasFPU(false), HasMul64(false), HasSqrt(false)
HasPatCmp(false), HasFPU(false), HasESR(false), HasPVR(false),
HasMul64(false), HasSqrt(false), HasMMU(false)
{ {
std::string CPU = "v400";
MBlazeArchVersion = V400;
// Parse features string. // Parse features string.
ParseSubtargetFeatures(FS, CPU); std::string CPU = "mblaze";
CPU = ParseSubtargetFeatures(FS, CPU);
// Only use instruction scheduling if the selected CPU has an instruction
// itinerary (the default CPU is the only one that doesn't).
HasItin = CPU != "mblaze";
DEBUG(dbgs() << "CPU " << CPU << "(" << HasItin << ")\n");
// Compute the issue width of the MBlaze itineraries
computeIssueWidth();
} }
void MBlazeSubtarget::computeIssueWidth() {
InstrItins.IssueWidth = 1;
}
bool MBlazeSubtarget::
enablePostRAScheduler(CodeGenOpt::Level OptLevel,
TargetSubtarget::AntiDepBreakMode& Mode,
RegClassVector& CriticalPathRCs) const {
Mode = TargetSubtarget::ANTIDEP_CRITICAL;
CriticalPathRCs.clear();
CriticalPathRCs.push_back(&MBlaze::GPRRegClass);
return HasItin && OptLevel >= CodeGenOpt::Default;
}

37
lib/Target/MBlaze/MBlazeSubtarget.h
View File

@ -24,29 +24,14 @@ namespace llvm {
class MBlazeSubtarget : public TargetSubtarget { class MBlazeSubtarget : public TargetSubtarget {
protected: protected:
enum MBlazeArchEnum {
V400, V500, V600, V700, V710
};
// MBlaze architecture version
MBlazeArchEnum MBlazeArchVersion;
bool HasPipe3;
bool HasBarrel; bool HasBarrel;
bool HasDiv; bool HasDiv;
bool HasMul; bool HasMul;
bool HasFSL;
bool HasEFSL;
bool HasMSRSet;
bool HasException;
bool HasPatCmp; bool HasPatCmp;
bool HasFPU; bool HasFPU;
bool HasESR;
bool HasPVR;
bool HasMul64; bool HasMul64;
bool HasSqrt; bool HasSqrt;
bool HasMMU; bool HasItin;
InstrItineraryData InstrItins; InstrItineraryData InstrItins;
@ -61,18 +46,26 @@ public:
std::string ParseSubtargetFeatures(const std::string &FS, std::string ParseSubtargetFeatures(const std::string &FS,
const std::string &CPU); const std::string &CPU);
/// Compute the number of maximum number of issues per cycle for the
/// MBlaze scheduling itineraries.
void computeIssueWidth();
/// enablePostRAScheduler - True at 'More' optimization.
bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
TargetSubtarget::AntiDepBreakMode& Mode,
RegClassVector& CriticalPathRCs) const;
/// getInstrItins - Return the instruction itineraies based on subtarget.
const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
bool hasItin() const { return HasItin; }
bool hasPCMP() const { return HasPatCmp; }
bool hasFPU() const { return HasFPU; } bool hasFPU() const { return HasFPU; }
bool hasSqrt() const { return HasSqrt; } bool hasSqrt() const { return HasSqrt; }
bool hasMul() const { return HasMul; } bool hasMul() const { return HasMul; }
bool hasMul64() const { return HasMul64; } bool hasMul64() const { return HasMul64; }
bool hasDiv() const { return HasDiv; } bool hasDiv() const { return HasDiv; }
bool hasBarrel() const { return HasBarrel; } bool hasBarrel() const { return HasBarrel; }
bool isV400() const { return MBlazeArchVersion == V400; }
bool isV500() const { return MBlazeArchVersion == V500; }
bool isV600() const { return MBlazeArchVersion == V600; }
bool isV700() const { return MBlazeArchVersion == V700; }
bool isV710() const { return MBlazeArchVersion == V710; }
}; };
} // End llvm namespace } // End llvm namespace

3
lib/Target/MBlaze/MBlazeTargetMachine.cpp
View File

@ -87,7 +87,8 @@ MBlazeTargetMachine(const Target &T, const std::string &TT,
DataLayout("E-p:32:32:32-i8:8:8-i16:16:16"), DataLayout("E-p:32:32:32-i8:8:8-i16:16:16"),
InstrInfo(*this), InstrInfo(*this),
FrameLowering(Subtarget), FrameLowering(Subtarget),
TLInfo(*this), TSInfo(*this), ELFWriterInfo(*this) { TLInfo(*this), TSInfo(*this), ELFWriterInfo(*this),
InstrItins(Subtarget.getInstrItineraryData()) {
if (getRelocationModel() == Reloc::Default) { if (getRelocationModel() == Reloc::Default) {
setRelocationModel(Reloc::Static); setRelocationModel(Reloc::Static);
} }

7
lib/Target/MBlaze/MBlazeTargetMachine.h
View File

@ -38,13 +38,18 @@ namespace llvm {
MBlazeSelectionDAGInfo TSInfo; MBlazeSelectionDAGInfo TSInfo;
MBlazeIntrinsicInfo IntrinsicInfo; MBlazeIntrinsicInfo IntrinsicInfo;
MBlazeELFWriterInfo ELFWriterInfo; MBlazeELFWriterInfo ELFWriterInfo;
InstrItineraryData InstrItins;
public: public:
MBlazeTargetMachine(const Target &T, const std::string &TT, MBlazeTargetMachine(const Target &T, const std::string &TT,
const std::string &FS); const std::string &FS);
virtual const MBlazeInstrInfo *getInstrInfo() const virtual const MBlazeInstrInfo *getInstrInfo() const
{ return &InstrInfo; } { return &InstrInfo; }
virtual const InstrItineraryData *getInstrItineraryData() const
{ return &InstrItins; }
virtual const TargetFrameLowering *getFrameLowering() const virtual const TargetFrameLowering *getFrameLowering() const
{ return &FrameLowering; } { return &FrameLowering; }

7
lib/Target/MBlaze/TODO
View File

@ -9,8 +9,6 @@
needs to be examined more closely: needs to be examined more closely:
- The stack layout needs to be examined to make sure it meets - The stack layout needs to be examined to make sure it meets
the standard, especially in regards to var arg functions. the standard, especially in regards to var arg functions.
- The processor itineraries are copied from a different backend
and need to be updated to model the MicroBlaze correctly.
- Look at the MBlazeGenFastISel.inc stuff and make use of it - Look at the MBlazeGenFastISel.inc stuff and make use of it
if appropriate. if appropriate.
@ -18,9 +16,6 @@
There are a few things that need to be looked at: There are a few things that need to be looked at:
- There are some instructions that are not generated by the backend - There are some instructions that are not generated by the backend
and have not been tested as far as the parser is concerned. and have not been tested as far as the parser is concerned.
- The assembly parser does not use any MicroBlaze specific directives. - The assembly parser does not use many MicroBlaze specific directives.
I should investigate if there are MicroBlaze specific directive and, I should investigate if there are MicroBlaze specific directive and,
if there are, add them. if there are, add them.
- The instruction MFS and MTS use special names for some of the
special registers that can be accessed. These special register
names should be parsed by the assembly parser.

18
test/CodeGen/MBlaze/fsl.ll
View File

@ -3,7 +3,7 @@
; dynamic version of the instructions and that constant values use the ; dynamic version of the instructions and that constant values use the
; constant version of the instructions. ; constant version of the instructions.
; ;
; RUN: llc < %s -march=mblaze | FileCheck %s ; RUN: llc -O3 < %s -march=mblaze | FileCheck %s
declare i32 @llvm.mblaze.fsl.get(i32 %port) declare i32 @llvm.mblaze.fsl.get(i32 %port)
declare i32 @llvm.mblaze.fsl.aget(i32 %port) declare i32 @llvm.mblaze.fsl.aget(i32 %port)
@ -55,8 +55,7 @@ declare void @llvm.mblaze.fsl.tnaput(i32 %port)
declare void @llvm.mblaze.fsl.tncput(i32 %port) declare void @llvm.mblaze.fsl.tncput(i32 %port)
declare void @llvm.mblaze.fsl.tncaput(i32 %port) declare void @llvm.mblaze.fsl.tncaput(i32 %port)
define i32 @fsl_get(i32 %port) define void @fsl_get(i32 %port) {
{
; CHECK: fsl_get: ; CHECK: fsl_get:
%v0 = call i32 @llvm.mblaze.fsl.get(i32 %port) %v0 = call i32 @llvm.mblaze.fsl.get(i32 %port)
; CHECK: getd ; CHECK: getd
@ -122,12 +121,11 @@ define i32 @fsl_get(i32 %port)
; CHECK-NEXT: tnecgetd ; CHECK-NEXT: tnecgetd
%v31 = call i32 @llvm.mblaze.fsl.tnecaget(i32 %port) %v31 = call i32 @llvm.mblaze.fsl.tnecaget(i32 %port)
; CHECK-NEXT: tnecagetd ; CHECK-NEXT: tnecagetd
ret i32 1 ret void
; CHECK: rtsd ; CHECK: rtsd
} }
define i32 @fslc_get() define void @fslc_get() {
{
; CHECK: fslc_get: ; CHECK: fslc_get:
%v0 = call i32 @llvm.mblaze.fsl.get(i32 1) %v0 = call i32 @llvm.mblaze.fsl.get(i32 1)
; CHECK: get ; CHECK: get
@ -224,12 +222,11 @@ define i32 @fslc_get()
%v31 = call i32 @llvm.mblaze.fsl.tnecaget(i32 1) %v31 = call i32 @llvm.mblaze.fsl.tnecaget(i32 1)
; CHECK-NOT: tnecagetd ; CHECK-NOT: tnecagetd
; CHECK: tnecaget ; CHECK: tnecaget
ret i32 1 ret void
; CHECK: rtsd ; CHECK: rtsd
} }
define void @putfsl(i32 %value, i32 %port) define void @putfsl(i32 %value, i32 %port) {
{
; CHECK: putfsl: ; CHECK: putfsl:
call void @llvm.mblaze.fsl.put(i32 %value, i32 %port) call void @llvm.mblaze.fsl.put(i32 %value, i32 %port)
; CHECK: putd ; CHECK: putd
@ -267,8 +264,7 @@ define void @putfsl(i32 %value, i32 %port)
; CHECK: rtsd ; CHECK: rtsd
} }
define void @putfsl_const(i32 %value) define void @putfsl_const(i32 %value) {
{
; CHECK: putfsl_const: ; CHECK: putfsl_const:
call void @llvm.mblaze.fsl.put(i32 %value, i32 1) call void @llvm.mblaze.fsl.put(i32 %value, i32 1)
; CHECK-NOT: putd ; CHECK-NOT: putd

6
test/CodeGen/MBlaze/loop.ll
View File

@ -29,14 +29,12 @@ loop_inner_finish:
%inner.5 = add i32 %inner.2, 1 %inner.5 = add i32 %inner.2, 1
call i32 (i8*,...)* @printf( i8* getelementptr([19 x i8]* @MSG,i32 0,i32 0), call i32 (i8*,...)* @printf( i8* getelementptr([19 x i8]* @MSG,i32 0,i32 0),
i32 %inner.0, i32 %inner.1, i32 %inner.2 ) i32 %inner.0, i32 %inner.1, i32 %inner.2 )
; CHECK: brlid
; CHECK: addik {{.*, 1}}
%inner.6 = icmp eq i32 %inner.5, 100 %inner.6 = icmp eq i32 %inner.5, 100
; CHECK: cmp ; CHECK: cmp [[REG:r[0-9]*]]
br i1 %inner.6, label %loop_inner, label %loop_outer_finish br i1 %inner.6, label %loop_inner, label %loop_outer_finish
; CHECK: {{beq|bne}} ; CHECK: {{beqid|bneid}} [[REG]]
loop_outer_finish: loop_outer_finish:
%outer.1 = add i32 %outer.0, 1 %outer.1 = add i32 %outer.0, 1