mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-01 15:11:24 +00:00
Assign ordering to nodes created in ExpandNode. Only roughly 1/2 of the function
is finished. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91942 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
parent
92fdf4537b
commit
3dbcb55b40
@ -2220,6 +2220,7 @@ SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
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void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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SmallVectorImpl<SDValue> &Results) {
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DebugLoc dl = Node->getDebugLoc();
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unsigned Order = DAG.GetOrdering(Node);
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SDValue Tmp1, Tmp2, Tmp3, Tmp4;
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switch (Node->getOpcode()) {
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case ISD::CTPOP:
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@ -2227,9 +2228,12 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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case ISD::CTTZ:
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Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
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Results.push_back(Tmp1);
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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break;
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case ISD::BSWAP:
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Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
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Tmp1 = ExpandBSWAP(Node->getOperand(0), dl);
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Results.push_back(Tmp1);
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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break;
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case ISD::FRAMEADDR:
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case ISD::RETURNADDR:
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@ -2280,12 +2284,14 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
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Node->getValueType(0), dl);
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Results.push_back(Tmp1);
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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break;
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case ISD::FP_EXTEND:
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Tmp1 = EmitStackConvert(Node->getOperand(0),
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Node->getOperand(0).getValueType(),
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Node->getValueType(0), dl);
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Results.push_back(Tmp1);
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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break;
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case ISD::SIGN_EXTEND_INREG: {
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// NOTE: we could fall back on load/store here too for targets without
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@ -2302,8 +2308,14 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
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Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
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Node->getOperand(0), ShiftCst);
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Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
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Results.push_back(Tmp1);
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Tmp2 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
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Results.push_back(Tmp2);
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if (DisableScheduling) {
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DAG.AssignOrdering(Tmp1.getNode(), Order);
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DAG.AssignOrdering(Tmp2.getNode(), Order);
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}
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break;
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}
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case ISD::FP_ROUND_INREG: {
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@ -2317,6 +2329,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
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Node->getValueType(0), dl);
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Results.push_back(Tmp1);
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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break;
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}
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case ISD::SINT_TO_FP:
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@ -2324,6 +2337,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
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Node->getOperand(0), Node->getValueType(0), dl);
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Results.push_back(Tmp1);
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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break;
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case ISD::FP_TO_UINT: {
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SDValue True, False;
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@ -2332,19 +2346,35 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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const uint64_t zero[] = {0, 0};
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APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
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APInt x = APInt::getSignBit(NVT.getSizeInBits());
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(void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
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Tmp1 = DAG.getConstantFP(apf, VT);
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Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
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Node->getOperand(0),
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Tmp1, ISD::SETLT);
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if (DisableScheduling) DAG.AssignOrdering(Tmp2.getNode(), Order);
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True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
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False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
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DAG.getNode(ISD::FSUB, dl, VT,
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Node->getOperand(0), Tmp1));
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Tmp1 = DAG.getNode(ISD::FSUB, dl, VT, Node->getOperand(0), Tmp1);
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False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Tmp1);
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if (DisableScheduling) {
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DAG.AssignOrdering(Tmp1.getNode(), Order);
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DAG.AssignOrdering(True.getNode(), Order);
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DAG.AssignOrdering(False.getNode(), Order);
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}
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False = DAG.getNode(ISD::XOR, dl, NVT, False,
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DAG.getConstant(x, NVT));
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Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False);
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Results.push_back(Tmp1);
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if (DisableScheduling) {
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DAG.AssignOrdering(Tmp1.getNode(), Order);
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DAG.AssignOrdering(False.getNode(), Order);
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}
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break;
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}
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case ISD::VAARG: {
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@ -2353,16 +2383,31 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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Tmp1 = Node->getOperand(0);
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Tmp2 = Node->getOperand(1);
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SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0);
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// Increment the pointer, VAList, to the next vaarg
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Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
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DAG.getConstant(TLI.getTargetData()->
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getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
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getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
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TLI.getPointerTy()));
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// Store the incremented VAList to the legalized pointer
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Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0);
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Tmp4 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0);
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if (DisableScheduling) {
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DAG.AssignOrdering(Tmp3.getNode(), Order);
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DAG.AssignOrdering(Tmp4.getNode(), Order);
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}
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// Load the actual argument out of the pointer VAList
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Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0));
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Tmp1 = DAG.getLoad(VT, dl, Tmp4, VAList, NULL, 0);
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Results.push_back(Tmp1);
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Results.push_back(Results[0].getValue(1));
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if (DisableScheduling) {
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DAG.AssignOrdering(Tmp1.getNode(), Order);
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DAG.AssignOrdering(Results[0].getValue(1).getNode(), Order);
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}
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break;
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}
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case ISD::VACOPY: {
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@ -2372,8 +2417,14 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
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Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
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Node->getOperand(2), VS, 0);
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Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), VD, 0);
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Results.push_back(Tmp1);
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Tmp2 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), VD, 0);
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Results.push_back(Tmp2);
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if (DisableScheduling) {
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DAG.AssignOrdering(Tmp1.getNode(), Order);
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DAG.AssignOrdering(Tmp2.getNode(), Order);
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}
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break;
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}
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case ISD::EXTRACT_VECTOR_ELT:
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@ -2383,22 +2434,32 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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Node->getOperand(0));
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else
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Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
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Results.push_back(Tmp1);
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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break;
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case ISD::EXTRACT_SUBVECTOR:
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Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
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Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
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Results.push_back(Tmp1);
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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break;
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case ISD::CONCAT_VECTORS: {
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Results.push_back(ExpandVectorBuildThroughStack(Node));
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Tmp1 = ExpandVectorBuildThroughStack(Node);
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Results.push_back(Tmp1);
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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break;
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}
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case ISD::SCALAR_TO_VECTOR:
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Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
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Tmp1 = ExpandSCALAR_TO_VECTOR(Node);
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Results.push_back(Tmp1);
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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break;
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case ISD::INSERT_VECTOR_ELT:
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Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
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Node->getOperand(1),
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Node->getOperand(2), dl));
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Tmp1 = ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
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Node->getOperand(1),
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Node->getOperand(2), dl);
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Results.push_back(Tmp1);
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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break;
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case ISD::VECTOR_SHUFFLE: {
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SmallVector<int, 8> Mask;
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@ -2408,65 +2469,88 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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EVT EltVT = VT.getVectorElementType();
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unsigned NumElems = VT.getVectorNumElements();
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SmallVector<SDValue, 8> Ops;
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for (unsigned i = 0; i != NumElems; ++i) {
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if (Mask[i] < 0) {
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Ops.push_back(DAG.getUNDEF(EltVT));
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continue;
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}
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unsigned Idx = Mask[i];
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if (Idx < NumElems)
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Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
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Node->getOperand(0),
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DAG.getIntPtrConstant(Idx)));
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Tmp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
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Node->getOperand(0),
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DAG.getIntPtrConstant(Idx));
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else
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Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
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Node->getOperand(1),
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DAG.getIntPtrConstant(Idx - NumElems)));
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Tmp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
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Node->getOperand(1),
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DAG.getIntPtrConstant(Idx - NumElems));
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Ops.push_back(Tmp1);
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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}
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Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
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Results.push_back(Tmp1);
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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break;
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}
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case ISD::EXTRACT_ELEMENT: {
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EVT OpTy = Node->getOperand(0).getValueType();
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if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
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// 1 -> Hi
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Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
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DAG.getConstant(OpTy.getSizeInBits()/2,
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TLI.getShiftAmountTy()));
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
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} else {
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// 0 -> Lo
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Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
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Node->getOperand(0));
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}
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Results.push_back(Tmp1);
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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break;
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}
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case ISD::STACKSAVE:
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// Expand to CopyFromReg if the target set
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// StackPointerRegisterToSaveRestore.
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if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
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Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
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Node->getValueType(0)));
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Tmp1 = DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
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Node->getValueType(0));
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Results.push_back(Tmp1);
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Results.push_back(Results[0].getValue(1));
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if (DisableScheduling) {
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DAG.AssignOrdering(Tmp1.getNode(), Order);
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DAG.AssignOrdering(Results[0].getValue(1).getNode(), Order);
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}
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} else {
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Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
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Tmp1 = DAG.getUNDEF(Node->getValueType(0));
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Results.push_back(Tmp1);
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Results.push_back(Node->getOperand(0));
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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}
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break;
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case ISD::STACKRESTORE:
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// Expand to CopyToReg if the target set
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// StackPointerRegisterToSaveRestore.
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if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
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Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
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Node->getOperand(1)));
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} else {
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Results.push_back(Node->getOperand(0));
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}
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// Expand to CopyToReg if the target set StackPointerRegisterToSaveRestore.
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if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore())
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Tmp1 = DAG.getCopyToReg(Node->getOperand(0), dl, SP,
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Node->getOperand(1));
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else
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Tmp1 = Node->getOperand(0);
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Results.push_back(Tmp1);
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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break;
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case ISD::FCOPYSIGN:
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Results.push_back(ExpandFCOPYSIGN(Node));
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Tmp1 = ExpandFCOPYSIGN(Node);
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Results.push_back(Tmp1);
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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break;
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case ISD::FNEG:
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// Expand Y = FNEG(X) -> Y = SUB -0.0, X
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@ -2474,113 +2558,172 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
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Node->getOperand(0));
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Results.push_back(Tmp1);
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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break;
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case ISD::FABS: {
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// Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
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EVT VT = Node->getValueType(0);
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Tmp1 = Node->getOperand(0);
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Tmp2 = DAG.getConstantFP(0.0, VT);
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Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
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Tmp3 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
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Tmp1, Tmp2, ISD::SETUGT);
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Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
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Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
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Tmp4 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
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Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp3, Tmp1, Tmp4);
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Results.push_back(Tmp1);
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if (DisableScheduling) {
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DAG.AssignOrdering(Tmp1.getNode(), Order);
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DAG.AssignOrdering(Tmp3.getNode(), Order);
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DAG.AssignOrdering(Tmp4.getNode(), Order);
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}
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break;
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}
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case ISD::FSQRT:
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Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
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RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128));
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Tmp1 = ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
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RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
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Results.push_back(Tmp1);
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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break;
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case ISD::FSIN:
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Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
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RTLIB::SIN_F80, RTLIB::SIN_PPCF128));
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Tmp1 = ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
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RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
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Results.push_back(Tmp1);
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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break;
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case ISD::FCOS:
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Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
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RTLIB::COS_F80, RTLIB::COS_PPCF128));
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Tmp1 = ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
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RTLIB::COS_F80, RTLIB::COS_PPCF128);
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Results.push_back(Tmp1);
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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break;
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case ISD::FLOG:
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Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
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RTLIB::LOG_F80, RTLIB::LOG_PPCF128));
|
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Tmp1 = ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
|
||||
RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
|
||||
Results.push_back(Tmp1);
|
||||
if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
|
||||
break;
|
||||
case ISD::FLOG2:
|
||||
Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
|
||||
RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128));
|
||||
Tmp1 = ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
|
||||
RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
|
||||
Results.push_back(Tmp1);
|
||||
if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
|
||||
break;
|
||||
case ISD::FLOG10:
|
||||
Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
|
||||
RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128));
|
||||
Tmp1 = ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
|
||||
RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
|
||||
Results.push_back(Tmp1);
|
||||
if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
|
||||
break;
|
||||
case ISD::FEXP:
|
||||
Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
|
||||
RTLIB::EXP_F80, RTLIB::EXP_PPCF128));
|
||||
Tmp1 = ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
|
||||
RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
|
||||
Results.push_back(Tmp1);
|
||||
if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
|
||||
break;
|
||||
case ISD::FEXP2:
|
||||
Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
|
||||
RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128));
|
||||
Tmp1 = ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
|
||||
RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
|
||||
Results.push_back(Tmp1);
|
||||
if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
|
||||
break;
|
||||
case ISD::FTRUNC:
|
||||
Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
|
||||
RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128));
|
||||
Tmp1 = ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
|
||||
RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
|
||||
Results.push_back(Tmp1);
|
||||
if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
|
||||
break;
|
||||
case ISD::FFLOOR:
|
||||
Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
|
||||
RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128));
|
||||
Tmp1 = ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
|
||||
RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
|
||||
Results.push_back(Tmp1);
|
||||
if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
|
||||
break;
|
||||
case ISD::FCEIL:
|
||||
Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
|
||||
RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128));
|
||||
Tmp1 = ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
|
||||
RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
|
||||
Results.push_back(Tmp1);
|
||||
if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
|
||||
break;
|
||||
case ISD::FRINT:
|
||||
Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
|
||||
RTLIB::RINT_F80, RTLIB::RINT_PPCF128));
|
||||
Tmp1 = ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
|
||||
RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
|
||||
Results.push_back(Tmp1);
|
||||
if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
|
||||
break;
|
||||
case ISD::FNEARBYINT:
|
||||
Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
|
||||
RTLIB::NEARBYINT_F64,
|
||||
RTLIB::NEARBYINT_F80,
|
||||
RTLIB::NEARBYINT_PPCF128));
|
||||
Tmp1 = ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
|
||||
RTLIB::NEARBYINT_F64,
|
||||
RTLIB::NEARBYINT_F80,
|
||||
RTLIB::NEARBYINT_PPCF128);
|
||||
Results.push_back(Tmp1);
|
||||
if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
|
||||
break;
|
||||
case ISD::FPOWI:
|
||||
Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
|
||||
RTLIB::POWI_F80, RTLIB::POWI_PPCF128));
|
||||
Tmp1 = ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
|
||||
RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
|
||||
Results.push_back(Tmp1);
|
||||
if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
|
||||
break;
|
||||
case ISD::FPOW:
|
||||
Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
|
||||
RTLIB::POW_F80, RTLIB::POW_PPCF128));
|
||||
Tmp1 = ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
|
||||
RTLIB::POW_F80, RTLIB::POW_PPCF128);
|
||||
Results.push_back(Tmp1);
|
||||
if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
|
||||
break;
|
||||
case ISD::FDIV:
|
||||
Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
|
||||
RTLIB::DIV_F80, RTLIB::DIV_PPCF128));
|
||||
Tmp1 = ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
|
||||
RTLIB::DIV_F80, RTLIB::DIV_PPCF128);
|
||||
Results.push_back(Tmp1);
|
||||
if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
|
||||
break;
|
||||
case ISD::FREM:
|
||||
Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
|
||||
RTLIB::REM_F80, RTLIB::REM_PPCF128));
|
||||
Tmp1 = ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
|
||||
RTLIB::REM_F80, RTLIB::REM_PPCF128);
|
||||
Results.push_back(Tmp1);
|
||||
if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
|
||||
break;
|
||||
case ISD::ConstantFP: {
|
||||
ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
|
||||
// Check to see if this FP immediate is already legal.
|
||||
// If this is a legal constant, turn it into a TargetConstantFP node.
|
||||
// Check to see if this FP immediate is already legal. If this is a legal
|
||||
// constant, turn it into a TargetConstantFP node.
|
||||
if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
|
||||
Results.push_back(SDValue(Node, 0));
|
||||
Tmp1 = SDValue(Node, 0);
|
||||
else
|
||||
Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI));
|
||||
Tmp1 = ExpandConstantFP(CFP, true, DAG, TLI);
|
||||
|
||||
Results.push_back(Tmp1);
|
||||
if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
|
||||
break;
|
||||
}
|
||||
case ISD::EHSELECTION: {
|
||||
unsigned Reg = TLI.getExceptionSelectorRegister();
|
||||
assert(Reg && "Can't expand to unknown register!");
|
||||
Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
|
||||
Node->getValueType(0)));
|
||||
Tmp1 = DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
|
||||
Node->getValueType(0));
|
||||
Results.push_back(Tmp1);
|
||||
Results.push_back(Results[0].getValue(1));
|
||||
|
||||
if (DisableScheduling) {
|
||||
DAG.AssignOrdering(Tmp1.getNode(), Order);
|
||||
DAG.AssignOrdering(Results[0].getValue(1).getNode(), Order);
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
case ISD::EXCEPTIONADDR: {
|
||||
unsigned Reg = TLI.getExceptionAddressRegister();
|
||||
assert(Reg && "Can't expand to unknown register!");
|
||||
Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg,
|
||||
Node->getValueType(0)));
|
||||
Tmp1 = DAG.getCopyFromReg(Node->getOperand(0), dl, Reg,
|
||||
Node->getValueType(0));
|
||||
Results.push_back(Tmp1);
|
||||
Results.push_back(Results[0].getValue(1));
|
||||
|
||||
if (DisableScheduling) {
|
||||
DAG.AssignOrdering(Tmp1.getNode(), Order);
|
||||
DAG.AssignOrdering(Results[0].getValue(1).getNode(), Order);
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
case ISD::SUB: {
|
||||
@ -2590,8 +2733,16 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
|
||||
"Don't know how to expand this subtraction!");
|
||||
Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
|
||||
DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
|
||||
Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT));
|
||||
Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
|
||||
Tmp2 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT));
|
||||
Tmp3 = DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp2);
|
||||
Results.push_back(Tmp3);
|
||||
|
||||
if (DisableScheduling) {
|
||||
DAG.AssignOrdering(Tmp1.getNode(), Order);
|
||||
DAG.AssignOrdering(Tmp2.getNode(), Order);
|
||||
DAG.AssignOrdering(Tmp3.getNode(), Order);
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
case ISD::UREM:
|
||||
@ -2603,6 +2754,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
|
||||
unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
|
||||
Tmp2 = Node->getOperand(0);
|
||||
Tmp3 = Node->getOperand(1);
|
||||
|
||||
if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
|
||||
Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
|
||||
} else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
|
||||
@ -2621,6 +2773,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
|
||||
RTLIB::UREM_I16, RTLIB::UREM_I32,
|
||||
RTLIB::UREM_I64, RTLIB::UREM_I128);
|
||||
}
|
||||
|
||||
Results.push_back(Tmp1);
|
||||
break;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user