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More cool stuff for the dag combiner. We can now finally handle things
like turning: _foo: fctiwz f0, f1 stfd f0, -8(r1) lwz r2, -4(r1) rlwinm r3, r2, 0, 16, 31 blr into _foo: fctiwz f0,f1 stfd f0,-8(r1) lhz r3,-2(r1) blr Also removed an unncessary constraint from sra -> srl conversion, which should take care of hte only reason we would ever need to handle sra in MaskedValueIsZero, AFAIK. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23703 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -279,8 +279,6 @@ static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask,
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// Bit counting instructions can not set the high bits of the result
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// register. The max number of bits sets depends on the input.
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return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0;
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// TODO we could handle some SRA cases here.
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default: break;
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}
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return false;
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@ -1034,7 +1032,7 @@ SDOperand DAGCombiner::visitSRA(SDNode *N) {
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if (N1C && N1C->isNullValue())
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return N0;
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// If the sign bit is known to be zero, switch this to a SRL.
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if (N1C && MaskedValueIsZero(N0, (1ULL << (OpSizeInBits-1)), TLI))
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if (MaskedValueIsZero(N0, (1ULL << (OpSizeInBits-1)), TLI))
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return DAG.getNode(ISD::SRL, VT, N0, N1);
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return SDOperand();
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}
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@ -1196,6 +1194,14 @@ SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
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// fold (sext (sext x)) -> (sext x)
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if (N0.getOpcode() == ISD::SIGN_EXTEND)
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return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
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// fold (sext (load x)) -> (sextload x)
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if (N0.getOpcode() == ISD::LOAD && N0.Val->hasNUsesOfValue(1, 0)) {
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SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
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N0.getOperand(1), N0.getOperand(2),
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N0.getValueType());
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CombineTo(N0.Val, ExtLoad, ExtLoad.getOperand(0));
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return CombineTo(N, ExtLoad);
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}
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return SDOperand();
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}
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@ -1292,6 +1298,19 @@ SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
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// and the truncate
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return N0.getOperand(0);
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}
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// fold (truncate (load x)) -> (smaller load x)
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if (N0.getOpcode() == ISD::LOAD && N0.Val->hasNUsesOfValue(1, 0)) {
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assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) &&
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"Cannot truncate to larger type!");
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MVT::ValueType PtrType = N0.getOperand(1).getValueType();
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uint64_t PtrOff =
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(MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8;
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SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1),
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DAG.getConstant(PtrOff, PtrType));
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SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2));
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CombineTo(N0.Val, Load, Load.getOperand(0));
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return CombineTo(N, Load);
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}
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return SDOperand();
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}
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