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Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148721 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -618,13 +618,23 @@ X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned SegReg,
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return X86Operand::CreateMem(Disp, Start, End, Size);
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}
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} else if (getLexer().is(AsmToken::Integer)) {
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// Handle '[' number ']'
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const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
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if (getParser().ParseExpression(Disp, End)) return 0;
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if (getLexer().isNot(AsmToken::RBrac))
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return ErrorOperand(Start, "Expected ']' token!");
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int64_t Val = Parser.getTok().getIntVal();
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Parser.Lex();
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return X86Operand::CreateMem(Disp, Start, End, Size);
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SMLoc Loc = Parser.getTok().getLoc();
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if (getLexer().is(AsmToken::RBrac)) {
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// Handle '[' number ']'
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Parser.Lex();
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return X86Operand::CreateMem(MCConstantExpr::Create(Val, getContext()),
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Start, End, Size);
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} else if (getLexer().is(AsmToken::Star)) {
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// Handle '[' Scale*IndexReg ']'
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Parser.Lex();
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SMLoc IdxRegLoc = Parser.getTok().getLoc();
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if (ParseRegister(IndexReg, IdxRegLoc, End))
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return ErrorOperand(IdxRegLoc, "Expected register");
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Scale = Val;
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} else
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return ErrorOperand(Loc, "Unepxeted token");
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}
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if (getLexer().is(AsmToken::Plus) || getLexer().is(AsmToken::Minus)) {
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@ -56,5 +56,7 @@ _main:
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// CHECK: fld %st(0)
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fld ST(0)
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// CHECK: movl %fs:(%rdi), %eax
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mov EAX, DWORD PTR FS:[RDI]
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mov EAX, DWORD PTR FS:[RDI]
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// CHECK: leal (,%rdi,4), %r8d
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lea R8D, DWORD PTR [4*RDI]
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ret
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