diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h
index 99440aa450d..392a6847a9f 100644
--- a/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -147,7 +147,8 @@ namespace ISD {
     // the elements.  The order is count, type, op0, op1.  All vector opcodes,
     // including VLOAD and VConstant must currently have count and type as
     // their 1st and 2nd arguments.
-    VADD, VSUB, VMUL,
+    VADD, VSUB, VMUL, VSDIV, VUDIV,
+    VAND, VOR, VXOR,
 
     // MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing
     // an unsigned/signed value of type i[2*n], then return the top part.
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 2da993559f5..dd8a4f3851e 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -152,9 +152,14 @@ private:
 static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
   switch (VecOp) {
   default: assert(0 && "Don't know how to scalarize this opcode!");
-  case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
-  case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
-  case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
+  case ISD::VADD:  return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
+  case ISD::VSUB:  return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
+  case ISD::VMUL:  return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
+  case ISD::VSDIV: return MVT::isInteger(VT) ? ISD::SDIV: ISD::FDIV;
+  case ISD::VUDIV: return MVT::isInteger(VT) ? ISD::UDIV: ISD::FDIV;
+  case ISD::VAND:  return MVT::isInteger(VT) ? ISD::AND : 0;
+  case ISD::VOR:   return MVT::isInteger(VT) ? ISD::OR  : 0;
+  case ISD::VXOR:  return MVT::isInteger(VT) ? ISD::XOR : 0;
   }
 }
 
@@ -3646,7 +3651,12 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
   }
   case ISD::VADD:
   case ISD::VSUB:
-  case ISD::VMUL: {
+  case ISD::VMUL:
+  case ISD::VSDIV:
+  case ISD::VUDIV:
+  case ISD::VAND:
+  case ISD::VOR:
+  case ISD::VXOR: {
     unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(0))->getValue();
     MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
     MVT::ValueType TVT = (NumElements/2 > 1)
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index fea9b6e6dcf..3069465800c 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -496,15 +496,17 @@ public:
   }
   void visitDiv(User &I) {
     const Type *Ty = I.getType();
-    visitBinary(I, Ty->isSigned() ? ISD::SDIV : ISD::UDIV, ISD::FDIV, 0);
+    visitBinary(I,
+                Ty->isSigned() ? ISD::SDIV : ISD::UDIV, ISD::FDIV,
+                Ty->isSigned() ? ISD::VSDIV : ISD::VUDIV);
   }
   void visitRem(User &I) {
     const Type *Ty = I.getType();
     visitBinary(I, Ty->isSigned() ? ISD::SREM : ISD::UREM, ISD::FREM, 0);
   }
-  void visitAnd(User &I) { visitBinary(I, ISD::AND, 0, 0); }
-  void visitOr (User &I) { visitBinary(I, ISD::OR,  0, 0); }
-  void visitXor(User &I) { visitBinary(I, ISD::XOR, 0, 0); }
+  void visitAnd(User &I) { visitBinary(I, ISD::AND, 0, ISD::VAND); }
+  void visitOr (User &I) { visitBinary(I, ISD::OR,  0, ISD::VOR); }
+  void visitXor(User &I) { visitBinary(I, ISD::XOR, 0, ISD::VXOR); }
   void visitShl(User &I) { visitShift(I, ISD::SHL); }
   void visitShr(User &I) { 
     visitShift(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA);