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Add MLA alias for ARMv4 support.

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Fix MLA defs to use register class GPRnopc.
Add encoding tests for multiply instructions.
(Alias for MUL/SMLAL/UMLAL added by r199026.)

Patch by Zhaoshi.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199491 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Renato Golin committed 2014-01-17 13:53:08 +00:00
1 parent 825488c539
commit 3e2346341c
3 files changed
+54 -9
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lib/Target/ARM/ARMInstrInfo.td
+14 -9
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@@ -3632,21 +3632,22 @@ def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
Requires<[IsARM, NoV6, UseMulOps]>;
}
def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd),
(ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra),
IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
[(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
Requires<[IsARM, HasV6, UseMulOps]> {
[(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>,
Requires<[IsARM, HasV6, UseMulOps]> {
bits<4> Ra;
let Inst{15-12} = Ra;
}
let Constraints = "@earlyclobber $Rd" in
def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
(ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
4, IIC_iMAC32,
[(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
(MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
Requires<[IsARM, NoV6]>;
def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd),
(ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
pred:$p, cc_out:$s), 4, IIC_iMAC32,
[(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))],
(MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>,
Requires<[IsARM, NoV6]>;
def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
@@ -5583,6 +5584,10 @@ def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm",
(MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
Requires<[IsARM, NoV6]>;
def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra",
(MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
pred:$p, cc_out:$s)>,
Requires<[IsARM, NoV6]>;
def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
(SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
Requires<[IsARM, NoV6]>;
test/MC/ARM/directive-arch-armv4.s
+1
View File
@@ -32,6 +32,7 @@
@ Check that multiplication is supported
mul r4, r5, r6
mla r4, r5, r6, r3
smull r4, r5, r6, r3
umull r4, r5, r6, r3
smlal r4, r5, r6, r3
test/MC/ARM/mul-v4.s
+39
View File
@@ -0,0 +1,39 @@
@ PR17647: MUL/MLA/SMLAL/UMLAL should be avalaibe to IAS for ARMv4 and higher
@ RUN: llvm-mc < %s -triple armv4-unknown-unknown -show-encoding | FileCheck %s --check-prefix=ARMV4
@ ARMV4: mul r0, r1, r2 @ encoding: [0x91,0x02,0x00,0xe0]
@ ARMV4: muls r0, r1, r2 @ encoding: [0x91,0x02,0x10,0xe0]
@ ARMV4: mulne r0, r1, r2 @ encoding: [0x91,0x02,0x00,0x10]
@ ARMV4: mulseq r0, r1, r2 @ encoding: [0x91,0x02,0x10,0x00]
mul r0, r1, r2
muls r0, r1, r2
mulne r0, r1, r2
mulseq r0, r1, r2
@ ARMV4: mla r0, r1, r2, r3 @ encoding: [0x91,0x32,0x20,0xe0]
@ ARMV4: mlas r0, r1, r2, r3 @ encoding: [0x91,0x32,0x30,0xe0]
@ ARMV4: mlane r0, r1, r2, r3 @ encoding: [0x91,0x32,0x20,0x10]
@ ARMV4: mlaseq r0, r1, r2, r3 @ encoding: [0x91,0x32,0x30,0x00]
mla r0, r1, r2, r3
mlas r0, r1, r2, r3
mlane r0, r1, r2, r3
mlaseq r0, r1, r2, r3
@ ARMV4: smlal r2, r3, r0, r1 @ encoding: [0x90,0x21,0xe3,0xe0]
@ ARMV4: smlals r2, r3, r0, r1 @ encoding: [0x90,0x21,0xf3,0xe0]
@ ARMV4: smlalne r2, r3, r0, r1 @ encoding: [0x90,0x21,0xe3,0x10]
@ ARMV4: smlalseq r2, r3, r0, r1 @ encoding: [0x90,0x21,0xf3,0x00]
smlal r2,r3,r0,r1
smlals r2,r3,r0,r1
smlalne r2,r3,r0,r1
smlalseq r2,r3,r0,r1
@ ARMV4: umlal r2, r3, r0, r1 @ encoding: [0x90,0x21,0xa3,0xe0]
@ ARMV4: umlals r2, r3, r0, r1 @ encoding: [0x90,0x21,0xb3,0xe0]
@ ARMV4: umlalne r2, r3, r0, r1 @ encoding: [0x90,0x21,0xa3,0x10]
@ ARMV4: umlalseq r2, r3, r0, r1 @ encoding: [0x90,0x21,0xb3,0x00]
umlal r2,r3,r0,r1
umlals r2,r3,r0,r1
umlalne r2,r3,r0,r1
umlalseq r2,r3,r0,r1