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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-07-29 10:25:12 +00:00
Add FP versions of the binary operators, keeping the int and fp worlds seperate.
Though I have done extensive testing, it is possible that this will break things in configs I can't test. Please let me know if this causes a problem and I'll fix it ASAP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23505 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@@ -158,7 +158,7 @@ namespace {
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
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setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
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setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
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setOperationAction(ISD::SREM , MVT::f64 , Expand);
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setOperationAction(ISD::FREM , MVT::f64 , Expand);
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setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
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setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
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@@ -205,12 +205,12 @@ namespace {
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setOperationAction(ISD::FCOS , MVT::f64, Expand);
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setOperationAction(ISD::FABS , MVT::f64, Expand);
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setOperationAction(ISD::FNEG , MVT::f64, Expand);
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setOperationAction(ISD::SREM , MVT::f64, Expand);
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setOperationAction(ISD::FREM , MVT::f64, Expand);
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setOperationAction(ISD::FSIN , MVT::f32, Expand);
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setOperationAction(ISD::FCOS , MVT::f32, Expand);
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setOperationAction(ISD::FABS , MVT::f32, Expand);
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setOperationAction(ISD::FNEG , MVT::f32, Expand);
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setOperationAction(ISD::SREM , MVT::f32, Expand);
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setOperationAction(ISD::FREM , MVT::f32, Expand);
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addLegalFPImmediate(+0.0); // xorps / xorpd
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} else {
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@@ -2513,6 +2513,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
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}
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return Result;
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case ISD::FADD:
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case ISD::ADD:
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Op0 = N.getOperand(0);
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Op1 = N.getOperand(1);
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@@ -2703,6 +2704,8 @@ unsigned ISel::SelectExpr(SDOperand N) {
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return Result;
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}
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case ISD::FSUB:
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case ISD::FMUL:
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case ISD::SUB:
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case ISD::MUL:
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case ISD::AND:
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@@ -2810,7 +2813,9 @@ unsigned ISel::SelectExpr(SDOperand N) {
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}
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switch (Node->getOpcode()) {
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default: assert(0 && "Unreachable!");
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case ISD::FSUB:
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case ISD::SUB: Opc = X86ScalarSSE ? SSE_SUBTab[Opc] : SUBTab[Opc]; break;
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case ISD::FMUL:
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case ISD::MUL: Opc = X86ScalarSSE ? SSE_MULTab[Opc] : MULTab[Opc]; break;
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case ISD::AND: Opc = ANDTab[Opc]; break;
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case ISD::OR: Opc = ORTab[Opc]; break;
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@@ -2824,7 +2829,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
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}
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if (isFoldableLoad(Op0, Op1, true))
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if (Node->getOpcode() != ISD::SUB) {
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if (Node->getOpcode() != ISD::SUB && Node->getOpcode() != ISD::FSUB) {
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std::swap(Op0, Op1);
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goto FoldOps;
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} else {
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@@ -2860,7 +2865,9 @@ unsigned ISel::SelectExpr(SDOperand N) {
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}
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switch (Node->getOpcode()) {
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default: assert(0 && "Unreachable!");
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case ISD::FSUB:
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case ISD::SUB: Opc = X86ScalarSSE ? SSE_SUBTab[Opc] : SUBTab[Opc]; break;
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case ISD::FMUL:
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case ISD::MUL: Opc = X86ScalarSSE ? SSE_MULTab[Opc] : MULTab[Opc]; break;
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case ISD::AND: Opc = ANDTab[Opc]; break;
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case ISD::OR: Opc = ORTab[Opc]; break;
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@@ -2902,7 +2909,9 @@ unsigned ISel::SelectExpr(SDOperand N) {
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}
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switch (Node->getOpcode()) {
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default: assert(0 && "Unreachable!");
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case ISD::FSUB:
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case ISD::SUB: Opc = X86ScalarSSE ? SSE_SUBTab[Opc] : SUBTab[Opc]; break;
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case ISD::FMUL:
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case ISD::MUL: Opc = X86ScalarSSE ? SSE_MULTab[Opc] : MULTab[Opc]; break;
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case ISD::AND: Opc = ANDTab[Opc]; break;
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case ISD::OR: Opc = ORTab[Opc]; break;
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@@ -3006,6 +3015,8 @@ unsigned ISel::SelectExpr(SDOperand N) {
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N.getValueType(), Result);
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return Result;
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case ISD::FDIV:
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case ISD::FREM:
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case ISD::SDIV:
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case ISD::UDIV:
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case ISD::SREM:
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@@ -3013,7 +3024,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
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assert((N.getOpcode() != ISD::SREM || MVT::isInteger(N.getValueType())) &&
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"We don't support this operator!");
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if (N.getOpcode() == ISD::SDIV) {
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if (N.getOpcode() == ISD::SDIV || N.getOpcode() == ISD::FDIV) {
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// We can fold loads into FpDIVs, but not really into any others.
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if (N.getValueType() == MVT::f64 && !X86ScalarSSE) {
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// Check for reversed and unreversed DIV.
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@@ -3756,9 +3767,12 @@ bool ISel::TryToFoldLoadOpStore(SDNode *Node) {
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default:
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std::cerr << "CANNOT [mem] op= val: ";
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StVal.Val->dump(); std::cerr << "\n";
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case ISD::FMUL:
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case ISD::MUL:
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case ISD::FDIV:
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case ISD::SDIV:
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case ISD::UDIV:
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case ISD::FREM:
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case ISD::SREM:
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case ISD::UREM: return false;
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@@ -3837,7 +3851,8 @@ bool ISel::TryToFoldLoadOpStore(SDNode *Node) {
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// If we have [mem] = V op [mem], try to turn it into:
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// [mem] = [mem] op V.
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if (Op1 == TheLoad && StVal.getOpcode() != ISD::SUB &&
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if (Op1 == TheLoad &&
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StVal.getOpcode() != ISD::SUB && StVal.getOpcode() != ISD::FSUB &&
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StVal.getOpcode() != ISD::SHL && StVal.getOpcode() != ISD::SRA &&
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StVal.getOpcode() != ISD::SRL)
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std::swap(Op0, Op1);
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