mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-19 04:29:21 +00:00
Add FP versions of the binary operators, keeping the int and fp worlds seperate.
Though I have done extensive testing, it is possible that this will break things in configs I can't test. Please let me know if this causes a problem and I'll fix it ASAP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23505 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
01b3d73c20
commit
3e2bafd640
@ -68,8 +68,8 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
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setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
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setOperationAction(ISD::SEXTLOAD, MVT::i16, Expand);
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setOperationAction(ISD::SREM, MVT::f32, Expand);
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setOperationAction(ISD::SREM, MVT::f64, Expand);
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setOperationAction(ISD::FREM, MVT::f32, Expand);
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setOperationAction(ISD::FREM, MVT::f64, Expand);
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setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
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@ -1275,10 +1275,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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case ISD::SHL: Opc = Alpha::SL; break;
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case ISD::SRL: Opc = Alpha::SRL; break;
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case ISD::SRA: Opc = Alpha::SRA; break;
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case ISD::MUL:
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Opc = isFP ? (DestType == MVT::f64 ? Alpha::MULT : Alpha::MULS)
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: Alpha::MULQ;
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break;
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case ISD::MUL: Opc = Alpha::MULQ; break;
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};
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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@ -1288,25 +1285,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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case ISD::ADD:
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case ISD::SUB:
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if (isFP) {
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ConstantFPSDNode *CN;
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if (opcode == ISD::ADD)
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Opc = DestType == MVT::f64 ? Alpha::ADDT : Alpha::ADDS;
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else
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Opc = DestType == MVT::f64 ? Alpha::SUBT : Alpha::SUBS;
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if (opcode == ISD::SUB
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&& (CN = dyn_cast<ConstantFPSDNode>(N.getOperand(0)))
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&& (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
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{
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Tmp2).addReg(Tmp2);
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} else {
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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}
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return Result;
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} else {
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{
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bool isAdd = opcode == ISD::ADD;
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//first check for Scaled Adds and Subs!
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@ -1369,15 +1348,25 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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}
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return Result;
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}
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case ISD::FADD:
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case ISD::FSUB:
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case ISD::FMUL:
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case ISD::FDIV: {
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if (opcode == ISD::FADD)
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Opc = DestType == MVT::f64 ? Alpha::ADDT : Alpha::ADDS;
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else if (opcode == ISD::FSUB)
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Opc = DestType == MVT::f64 ? Alpha::SUBT : Alpha::SUBS;
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else if (opcode == ISD::FMUL)
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Opc = DestType == MVT::f64 ? Alpha::MULT : Alpha::MULS;
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else
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Opc = DestType == MVT::f64 ? Alpha::DIVT : Alpha::DIVS;
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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return Result;
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}
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case ISD::SDIV:
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if (isFP) {
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, DestType == MVT::f64 ? Alpha::DIVT : Alpha::DIVS, 2, Result)
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.addReg(Tmp1).addReg(Tmp2);
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return Result;
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} else {
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{
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//check if we can convert into a shift!
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if (isSIntImmediate(N.getOperand(1), SImm) &&
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SImm != 0 && isPowerOf2_64(llabs(SImm))) {
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@ -72,8 +72,8 @@ namespace {
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setOperationAction(ISD::SEXTLOAD , MVT::i16 , Expand);
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setOperationAction(ISD::SEXTLOAD , MVT::i32 , Expand);
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setOperationAction(ISD::SREM , MVT::f32 , Expand);
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setOperationAction(ISD::SREM , MVT::f64 , Expand);
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setOperationAction(ISD::FREM , MVT::f32 , Expand);
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setOperationAction(ISD::FREM , MVT::f64 , Expand);
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setOperationAction(ISD::UREM , MVT::f32 , Expand);
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setOperationAction(ISD::UREM , MVT::f64 , Expand);
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@ -1241,11 +1241,11 @@ unsigned ISel::SelectExpr(SDOperand N) {
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return Result;
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}
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case ISD::ADD: {
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if(DestType == MVT::f64 && N.getOperand(0).getOpcode() == ISD::MUL &&
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N.getOperand(0).Val->hasOneUse()) { // if we can fold this add
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// into an fma, do so:
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// ++FusedFP; // Statistic
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case ISD::FADD: {
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if (N.getOperand(0).getOpcode() == ISD::FMUL &&
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N.getOperand(0).Val->hasOneUse()) { // if we can fold this add
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// into an fma, do so:
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// ++FusedFP; // Statistic
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Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
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Tmp3 = SelectExpr(N.getOperand(1));
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@ -1253,7 +1253,15 @@ unsigned ISel::SelectExpr(SDOperand N) {
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return Result; // early exit
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}
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if(DestType != MVT::f64 && N.getOperand(0).getOpcode() == ISD::SHL &&
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//else, fallthrough:
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, IA64::FADD, 2, Result).addReg(Tmp1).addReg(Tmp2);
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return Result;
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}
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case ISD::ADD: {
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if (N.getOperand(0).getOpcode() == ISD::SHL &&
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N.getOperand(0).Val->hasOneUse()) { // if we might be able to fold
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// this add into a shladd, try:
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ConstantSDNode *CSD = NULL;
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@ -1273,75 +1281,71 @@ unsigned ISel::SelectExpr(SDOperand N) {
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//else, fallthrough:
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Tmp1 = SelectExpr(N.getOperand(0));
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if(DestType != MVT::f64) { // integer addition:
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switch (ponderIntegerAdditionWith(N.getOperand(1), Tmp3)) {
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case 1: // adding a constant that's 14 bits
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BuildMI(BB, IA64::ADDIMM14, 2, Result).addReg(Tmp1).addSImm(Tmp3);
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return Result; // early exit
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} // fallthrough and emit a reg+reg ADD:
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, IA64::ADD, 2, Result).addReg(Tmp1).addReg(Tmp2);
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} else { // this is a floating point addition
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, IA64::FADD, 2, Result).addReg(Tmp1).addReg(Tmp2);
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}
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switch (ponderIntegerAdditionWith(N.getOperand(1), Tmp3)) {
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case 1: // adding a constant that's 14 bits
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BuildMI(BB, IA64::ADDIMM14, 2, Result).addReg(Tmp1).addSImm(Tmp3);
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return Result; // early exit
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} // fallthrough and emit a reg+reg ADD:
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, IA64::ADD, 2, Result).addReg(Tmp1).addReg(Tmp2);
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return Result;
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}
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case ISD::FMUL:
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, IA64::FMPY, 2, Result).addReg(Tmp1).addReg(Tmp2);
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return Result;
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case ISD::MUL: {
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if(DestType != MVT::f64) { // TODO: speed!
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// TODO: speed!
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/* FIXME if(N.getOperand(1).getOpcode() != ISD::Constant) { // if not a const mul
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*/
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// boring old integer multiply with xma
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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unsigned TempFR1=MakeReg(MVT::f64);
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unsigned TempFR2=MakeReg(MVT::f64);
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unsigned TempFR3=MakeReg(MVT::f64);
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BuildMI(BB, IA64::SETFSIG, 1, TempFR1).addReg(Tmp1);
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BuildMI(BB, IA64::SETFSIG, 1, TempFR2).addReg(Tmp2);
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BuildMI(BB, IA64::XMAL, 1, TempFR3).addReg(TempFR1).addReg(TempFR2)
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.addReg(IA64::F0);
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BuildMI(BB, IA64::GETFSIG, 1, Result).addReg(TempFR3);
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return Result; // early exit
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/* FIXME } else { // we are multiplying by an integer constant! yay
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return Reg = SelectExpr(BuildConstmulSequence(N)); // avert your eyes!
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} */
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}
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else { // floating point multiply
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// boring old integer multiply with xma
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, IA64::FMPY, 2, Result).addReg(Tmp1).addReg(Tmp2);
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return Result;
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}
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unsigned TempFR1=MakeReg(MVT::f64);
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unsigned TempFR2=MakeReg(MVT::f64);
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unsigned TempFR3=MakeReg(MVT::f64);
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BuildMI(BB, IA64::SETFSIG, 1, TempFR1).addReg(Tmp1);
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BuildMI(BB, IA64::SETFSIG, 1, TempFR2).addReg(Tmp2);
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BuildMI(BB, IA64::XMAL, 1, TempFR3).addReg(TempFR1).addReg(TempFR2)
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.addReg(IA64::F0);
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BuildMI(BB, IA64::GETFSIG, 1, Result).addReg(TempFR3);
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return Result; // early exit
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/* FIXME } else { // we are multiplying by an integer constant! yay
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return Reg = SelectExpr(BuildConstmulSequence(N)); // avert your eyes!
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} */
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}
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case ISD::SUB: {
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if(DestType == MVT::f64 && N.getOperand(0).getOpcode() == ISD::MUL &&
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case ISD::FSUB:
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if(N.getOperand(0).getOpcode() == ISD::FMUL &&
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N.getOperand(0).Val->hasOneUse()) { // if we can fold this sub
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// into an fms, do so:
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// ++FusedFP; // Statistic
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// ++FusedFP; // Statistic
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Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
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Tmp3 = SelectExpr(N.getOperand(1));
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BuildMI(BB, IA64::FMS, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
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return Result; // early exit
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}
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Tmp2 = SelectExpr(N.getOperand(1));
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if(DestType != MVT::f64) { // integer subtraction:
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switch (ponderIntegerSubtractionFrom(N.getOperand(0), Tmp3)) {
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case 1: // subtracting *from* an 8 bit constant:
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BuildMI(BB, IA64::SUBIMM8, 2, Result).addSImm(Tmp3).addReg(Tmp2);
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return Result; // early exit
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} // fallthrough and emit a reg+reg SUB:
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Tmp1 = SelectExpr(N.getOperand(0));
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BuildMI(BB, IA64::SUB, 2, Result).addReg(Tmp1).addReg(Tmp2);
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} else { // this is a floating point subtraction
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Tmp1 = SelectExpr(N.getOperand(0));
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BuildMI(BB, IA64::FSUB, 2, Result).addReg(Tmp1).addReg(Tmp2);
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}
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Tmp1 = SelectExpr(N.getOperand(0));
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BuildMI(BB, IA64::FSUB, 2, Result).addReg(Tmp1).addReg(Tmp2);
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return Result;
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case ISD::SUB: {
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Tmp2 = SelectExpr(N.getOperand(1));
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switch (ponderIntegerSubtractionFrom(N.getOperand(0), Tmp3)) {
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case 1: // subtracting *from* an 8 bit constant:
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BuildMI(BB, IA64::SUBIMM8, 2, Result).addSImm(Tmp3).addReg(Tmp2);
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return Result; // early exit
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} // fallthrough and emit a reg+reg SUB:
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Tmp1 = SelectExpr(N.getOperand(0));
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BuildMI(BB, IA64::SUB, 2, Result).addReg(Tmp1).addReg(Tmp2);
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return Result;
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}
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@ -1584,6 +1588,7 @@ pC = pA OR pB
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return Result;
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}
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case ISD::FDIV:
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case ISD::SDIV:
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case ISD::UDIV:
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case ISD::SREM:
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@ -1601,8 +1606,10 @@ pC = pA OR pB
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bool isSigned=false;
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switch(N.getOpcode()) {
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case ISD::FDIV:
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case ISD::SDIV: isModulus=false; isSigned=true; break;
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case ISD::UDIV: isModulus=false; isSigned=false; break;
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case ISD::FREM:
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case ISD::SREM: isModulus=true; isSigned=true; break;
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case ISD::UREM: isModulus=true; isSigned=false; break;
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}
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@ -158,7 +158,7 @@ namespace {
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
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setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
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setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
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setOperationAction(ISD::SREM , MVT::f64 , Expand);
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setOperationAction(ISD::FREM , MVT::f64 , Expand);
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setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
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setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
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@ -205,12 +205,12 @@ namespace {
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setOperationAction(ISD::FCOS , MVT::f64, Expand);
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setOperationAction(ISD::FABS , MVT::f64, Expand);
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setOperationAction(ISD::FNEG , MVT::f64, Expand);
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setOperationAction(ISD::SREM , MVT::f64, Expand);
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setOperationAction(ISD::FREM , MVT::f64, Expand);
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setOperationAction(ISD::FSIN , MVT::f32, Expand);
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setOperationAction(ISD::FCOS , MVT::f32, Expand);
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setOperationAction(ISD::FABS , MVT::f32, Expand);
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setOperationAction(ISD::FNEG , MVT::f32, Expand);
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setOperationAction(ISD::SREM , MVT::f32, Expand);
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setOperationAction(ISD::FREM , MVT::f32, Expand);
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addLegalFPImmediate(+0.0); // xorps / xorpd
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} else {
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@ -2513,6 +2513,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
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}
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return Result;
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case ISD::FADD:
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case ISD::ADD:
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Op0 = N.getOperand(0);
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Op1 = N.getOperand(1);
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@ -2703,6 +2704,8 @@ unsigned ISel::SelectExpr(SDOperand N) {
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return Result;
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}
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case ISD::FSUB:
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case ISD::FMUL:
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case ISD::SUB:
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case ISD::MUL:
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case ISD::AND:
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@ -2810,7 +2813,9 @@ unsigned ISel::SelectExpr(SDOperand N) {
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}
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switch (Node->getOpcode()) {
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default: assert(0 && "Unreachable!");
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case ISD::FSUB:
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case ISD::SUB: Opc = X86ScalarSSE ? SSE_SUBTab[Opc] : SUBTab[Opc]; break;
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case ISD::FMUL:
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case ISD::MUL: Opc = X86ScalarSSE ? SSE_MULTab[Opc] : MULTab[Opc]; break;
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case ISD::AND: Opc = ANDTab[Opc]; break;
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case ISD::OR: Opc = ORTab[Opc]; break;
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@ -2824,7 +2829,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
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}
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if (isFoldableLoad(Op0, Op1, true))
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if (Node->getOpcode() != ISD::SUB) {
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if (Node->getOpcode() != ISD::SUB && Node->getOpcode() != ISD::FSUB) {
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std::swap(Op0, Op1);
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goto FoldOps;
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} else {
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@ -2860,7 +2865,9 @@ unsigned ISel::SelectExpr(SDOperand N) {
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}
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switch (Node->getOpcode()) {
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default: assert(0 && "Unreachable!");
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case ISD::FSUB:
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case ISD::SUB: Opc = X86ScalarSSE ? SSE_SUBTab[Opc] : SUBTab[Opc]; break;
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case ISD::FMUL:
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case ISD::MUL: Opc = X86ScalarSSE ? SSE_MULTab[Opc] : MULTab[Opc]; break;
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case ISD::AND: Opc = ANDTab[Opc]; break;
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case ISD::OR: Opc = ORTab[Opc]; break;
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@ -2902,7 +2909,9 @@ unsigned ISel::SelectExpr(SDOperand N) {
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}
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switch (Node->getOpcode()) {
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default: assert(0 && "Unreachable!");
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case ISD::FSUB:
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case ISD::SUB: Opc = X86ScalarSSE ? SSE_SUBTab[Opc] : SUBTab[Opc]; break;
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case ISD::FMUL:
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case ISD::MUL: Opc = X86ScalarSSE ? SSE_MULTab[Opc] : MULTab[Opc]; break;
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case ISD::AND: Opc = ANDTab[Opc]; break;
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case ISD::OR: Opc = ORTab[Opc]; break;
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@ -3006,6 +3015,8 @@ unsigned ISel::SelectExpr(SDOperand N) {
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N.getValueType(), Result);
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return Result;
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case ISD::FDIV:
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case ISD::FREM:
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case ISD::SDIV:
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case ISD::UDIV:
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case ISD::SREM:
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@ -3013,7 +3024,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
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assert((N.getOpcode() != ISD::SREM || MVT::isInteger(N.getValueType())) &&
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"We don't support this operator!");
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if (N.getOpcode() == ISD::SDIV) {
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if (N.getOpcode() == ISD::SDIV || N.getOpcode() == ISD::FDIV) {
|
||||
// We can fold loads into FpDIVs, but not really into any others.
|
||||
if (N.getValueType() == MVT::f64 && !X86ScalarSSE) {
|
||||
// Check for reversed and unreversed DIV.
|
||||
@ -3756,9 +3767,12 @@ bool ISel::TryToFoldLoadOpStore(SDNode *Node) {
|
||||
default:
|
||||
std::cerr << "CANNOT [mem] op= val: ";
|
||||
StVal.Val->dump(); std::cerr << "\n";
|
||||
case ISD::FMUL:
|
||||
case ISD::MUL:
|
||||
case ISD::FDIV:
|
||||
case ISD::SDIV:
|
||||
case ISD::UDIV:
|
||||
case ISD::FREM:
|
||||
case ISD::SREM:
|
||||
case ISD::UREM: return false;
|
||||
|
||||
@ -3837,7 +3851,8 @@ bool ISel::TryToFoldLoadOpStore(SDNode *Node) {
|
||||
|
||||
// If we have [mem] = V op [mem], try to turn it into:
|
||||
// [mem] = [mem] op V.
|
||||
if (Op1 == TheLoad && StVal.getOpcode() != ISD::SUB &&
|
||||
if (Op1 == TheLoad &&
|
||||
StVal.getOpcode() != ISD::SUB && StVal.getOpcode() != ISD::FSUB &&
|
||||
StVal.getOpcode() != ISD::SHL && StVal.getOpcode() != ISD::SRA &&
|
||||
StVal.getOpcode() != ISD::SRL)
|
||||
std::swap(Op0, Op1);
|
||||
|
Loading…
Reference in New Issue
Block a user