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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-26 23:29:22 +00:00
Refactor code to select NEON VLD intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84117 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson
parent
5db2c52270
commit
3e36f13ba7
@ -126,6 +126,13 @@ private:
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/// SelectDYN_ALLOC - Select dynamic alloc for Thumb.
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SDNode *SelectDYN_ALLOC(SDValue Op);
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/// SelectVLD - Select NEON load intrinsics. NumVecs should
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/// be 2, 3 or 4. The opcode arrays specify the instructions used for
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/// loads of D registers and even subregs and odd subregs of Q registers.
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/// For NumVecs == 2, QOpcodes1 is not used.
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SDNode *SelectVLD(SDValue Op, unsigned NumVecs, unsigned *DOpcodes,
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unsigned *QOpcodes0, unsigned *QOpcodes1);
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/// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
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/// be 2, 3 or 4. The opcode arrays specify the instructions used for
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/// load/store of D registers and even subregs and odd subregs of Q registers.
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@ -990,6 +997,94 @@ static EVT GetNEONSubregVT(EVT VT) {
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}
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}
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SDNode *ARMDAGToDAGISel::SelectVLD(SDValue Op, unsigned NumVecs,
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unsigned *DOpcodes, unsigned *QOpcodes0,
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unsigned *QOpcodes1) {
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assert(NumVecs >=2 && NumVecs <= 4 && "VLD NumVecs out-of-range");
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SDNode *N = Op.getNode();
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DebugLoc dl = N->getDebugLoc();
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
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return NULL;
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SDValue Chain = N->getOperand(0);
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EVT VT = N->getValueType(0);
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bool is64BitVector = VT.is64BitVector();
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unsigned OpcodeIndex;
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switch (VT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled vld type");
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// Double-register operations:
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case MVT::v8i8: OpcodeIndex = 0; break;
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case MVT::v4i16: OpcodeIndex = 1; break;
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case MVT::v2f32:
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case MVT::v2i32: OpcodeIndex = 2; break;
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case MVT::v1i64: OpcodeIndex = 3; break;
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// Quad-register operations:
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case MVT::v16i8: OpcodeIndex = 0; break;
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case MVT::v8i16: OpcodeIndex = 1; break;
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case MVT::v4f32:
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case MVT::v4i32: OpcodeIndex = 2; break;
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}
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if (is64BitVector) {
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unsigned Opc = DOpcodes[OpcodeIndex];
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
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std::vector<EVT> ResTys(NumVecs, VT);
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ResTys.push_back(MVT::Other);
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return CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 4);
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}
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EVT RegVT = GetNEONSubregVT(VT);
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if (NumVecs == 2) {
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// Quad registers are directly supported for VLD2,
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// loading 2 pairs of D regs.
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unsigned Opc = QOpcodes0[OpcodeIndex];
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
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std::vector<EVT> ResTys(4, VT);
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ResTys.push_back(MVT::Other);
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SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 4);
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Chain = SDValue(VLd, 4);
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// Combine the even and odd subregs to produce the result.
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for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
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SDNode *Q = PairDRegs(VT, SDValue(VLd, 2*Vec), SDValue(VLd, 2*Vec+1));
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ReplaceUses(SDValue(N, Vec), SDValue(Q, 0));
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}
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} else {
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// Otherwise, quad registers are loaded with two separate instructions,
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// where one loads the even registers and the other loads the odd registers.
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// Enable writeback to the address register.
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MemOpc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(true), MVT::i32);
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std::vector<EVT> ResTys(NumVecs, RegVT);
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ResTys.push_back(MemAddr.getValueType());
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ResTys.push_back(MVT::Other);
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// Load the even subreg.
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unsigned Opc = QOpcodes0[OpcodeIndex];
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const SDValue OpsA[] = { MemAddr, MemUpdate, MemOpc, Chain };
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SDNode *VLdA = CurDAG->getMachineNode(Opc, dl, ResTys, OpsA, 4);
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Chain = SDValue(VLdA, NumVecs+1);
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// Load the odd subreg.
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Opc = QOpcodes1[OpcodeIndex];
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const SDValue OpsB[] = { SDValue(VLdA, NumVecs), MemUpdate, MemOpc, Chain };
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SDNode *VLdB = CurDAG->getMachineNode(Opc, dl, ResTys, OpsB, 4);
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Chain = SDValue(VLdB, NumVecs+1);
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// Combine the even and odd subregs to produce the result.
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for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
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SDNode *Q = PairDRegs(VT, SDValue(VLdA, Vec), SDValue(VLdB, Vec));
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ReplaceUses(SDValue(N, Vec), SDValue(Q, 0));
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}
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}
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ReplaceUses(SDValue(N, NumVecs), Chain);
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return NULL;
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}
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SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDValue Op, bool IsLoad,
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unsigned NumVecs, unsigned *DOpcodes,
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unsigned *QOpcodes0,
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@ -1525,159 +1620,26 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
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break;
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case Intrinsic::arm_neon_vld2: {
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
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return NULL;
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SDValue Chain = N->getOperand(0);
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if (VT.is64BitVector()) {
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switch (VT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled vld2 type");
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case MVT::v8i8: Opc = ARM::VLD2d8; break;
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case MVT::v4i16: Opc = ARM::VLD2d16; break;
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case MVT::v2f32:
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case MVT::v2i32: Opc = ARM::VLD2d32; break;
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case MVT::v1i64: Opc = ARM::VLD2d64; break;
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}
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
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return CurDAG->getMachineNode(Opc, dl, VT, VT, MVT::Other, Ops, 4);
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}
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// Quad registers are loaded as pairs of double registers.
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EVT RegVT;
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switch (VT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled vld2 type");
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case MVT::v16i8: Opc = ARM::VLD2q8; RegVT = MVT::v8i8; break;
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case MVT::v8i16: Opc = ARM::VLD2q16; RegVT = MVT::v4i16; break;
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case MVT::v4f32: Opc = ARM::VLD2q32; RegVT = MVT::v2f32; break;
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case MVT::v4i32: Opc = ARM::VLD2q32; RegVT = MVT::v2i32; break;
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}
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
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std::vector<EVT> ResTys(4, RegVT);
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ResTys.push_back(MVT::Other);
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SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 4);
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SDNode *Q0 = PairDRegs(VT, SDValue(VLd, 0), SDValue(VLd, 1));
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SDNode *Q1 = PairDRegs(VT, SDValue(VLd, 2), SDValue(VLd, 3));
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ReplaceUses(SDValue(N, 0), SDValue(Q0, 0));
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ReplaceUses(SDValue(N, 1), SDValue(Q1, 0));
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ReplaceUses(SDValue(N, 2), SDValue(VLd, 4));
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return NULL;
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unsigned DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16,
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ARM::VLD2d32, ARM::VLD2d64 };
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unsigned QOpcodes[] = { ARM::VLD2q8, ARM::VLD2q16, ARM::VLD2q32 };
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return SelectVLD(Op, 2, DOpcodes, QOpcodes, 0);
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}
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case Intrinsic::arm_neon_vld3: {
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
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return NULL;
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SDValue Chain = N->getOperand(0);
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if (VT.is64BitVector()) {
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switch (VT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled vld3 type");
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case MVT::v8i8: Opc = ARM::VLD3d8; break;
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case MVT::v4i16: Opc = ARM::VLD3d16; break;
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case MVT::v2f32:
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case MVT::v2i32: Opc = ARM::VLD3d32; break;
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case MVT::v1i64: Opc = ARM::VLD3d64; break;
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}
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
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return CurDAG->getMachineNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 4);
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}
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// Quad registers are loaded with two separate instructions, where one
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// loads the even registers and the other loads the odd registers.
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EVT RegVT;
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unsigned Opc2 = 0;
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switch (VT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled vld3 type");
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case MVT::v16i8:
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Opc = ARM::VLD3q8a; Opc2 = ARM::VLD3q8b; RegVT = MVT::v8i8; break;
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case MVT::v8i16:
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Opc = ARM::VLD3q16a; Opc2 = ARM::VLD3q16b; RegVT = MVT::v4i16; break;
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case MVT::v4f32:
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Opc = ARM::VLD3q32a; Opc2 = ARM::VLD3q32b; RegVT = MVT::v2f32; break;
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case MVT::v4i32:
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Opc = ARM::VLD3q32a; Opc2 = ARM::VLD3q32b; RegVT = MVT::v2i32; break;
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}
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// Enable writeback to the address register.
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MemOpc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(true), MVT::i32);
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std::vector<EVT> ResTys(3, RegVT);
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ResTys.push_back(MemAddr.getValueType());
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ResTys.push_back(MVT::Other);
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const SDValue OpsA[] = { MemAddr, MemUpdate, MemOpc, Chain };
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SDNode *VLdA = CurDAG->getMachineNode(Opc, dl, ResTys, OpsA, 4);
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Chain = SDValue(VLdA, 4);
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const SDValue OpsB[] = { SDValue(VLdA, 3), MemUpdate, MemOpc, Chain };
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SDNode *VLdB = CurDAG->getMachineNode(Opc2, dl, ResTys, OpsB, 4);
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Chain = SDValue(VLdB, 4);
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SDNode *Q0 = PairDRegs(VT, SDValue(VLdA, 0), SDValue(VLdB, 0));
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SDNode *Q1 = PairDRegs(VT, SDValue(VLdA, 1), SDValue(VLdB, 1));
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SDNode *Q2 = PairDRegs(VT, SDValue(VLdA, 2), SDValue(VLdB, 2));
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ReplaceUses(SDValue(N, 0), SDValue(Q0, 0));
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ReplaceUses(SDValue(N, 1), SDValue(Q1, 0));
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ReplaceUses(SDValue(N, 2), SDValue(Q2, 0));
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ReplaceUses(SDValue(N, 3), Chain);
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return NULL;
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unsigned DOpcodes[] = { ARM::VLD3d8, ARM::VLD3d16,
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ARM::VLD3d32, ARM::VLD3d64 };
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unsigned QOpcodes0[] = { ARM::VLD3q8a, ARM::VLD3q16a, ARM::VLD3q32a };
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unsigned QOpcodes1[] = { ARM::VLD3q8b, ARM::VLD3q16b, ARM::VLD3q32b };
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return SelectVLD(Op, 3, DOpcodes, QOpcodes0, QOpcodes1);
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}
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case Intrinsic::arm_neon_vld4: {
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
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return NULL;
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SDValue Chain = N->getOperand(0);
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if (VT.is64BitVector()) {
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switch (VT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled vld4 type");
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case MVT::v8i8: Opc = ARM::VLD4d8; break;
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case MVT::v4i16: Opc = ARM::VLD4d16; break;
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case MVT::v2f32:
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case MVT::v2i32: Opc = ARM::VLD4d32; break;
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case MVT::v1i64: Opc = ARM::VLD4d64; break;
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}
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
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std::vector<EVT> ResTys(4, VT);
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ResTys.push_back(MVT::Other);
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return CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 4);
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}
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// Quad registers are loaded with two separate instructions, where one
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// loads the even registers and the other loads the odd registers.
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EVT RegVT;
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unsigned Opc2 = 0;
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switch (VT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled vld4 type");
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case MVT::v16i8:
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Opc = ARM::VLD4q8a; Opc2 = ARM::VLD4q8b; RegVT = MVT::v8i8; break;
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case MVT::v8i16:
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Opc = ARM::VLD4q16a; Opc2 = ARM::VLD4q16b; RegVT = MVT::v4i16; break;
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case MVT::v4f32:
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Opc = ARM::VLD4q32a; Opc2 = ARM::VLD4q32b; RegVT = MVT::v2f32; break;
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case MVT::v4i32:
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Opc = ARM::VLD4q32a; Opc2 = ARM::VLD4q32b; RegVT = MVT::v2i32; break;
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}
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// Enable writeback to the address register.
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MemOpc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(true), MVT::i32);
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std::vector<EVT> ResTys(4, RegVT);
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ResTys.push_back(MemAddr.getValueType());
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ResTys.push_back(MVT::Other);
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const SDValue OpsA[] = { MemAddr, MemUpdate, MemOpc, Chain };
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SDNode *VLdA = CurDAG->getMachineNode(Opc, dl, ResTys, OpsA, 4);
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Chain = SDValue(VLdA, 5);
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const SDValue OpsB[] = { SDValue(VLdA, 4), MemUpdate, MemOpc, Chain };
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SDNode *VLdB = CurDAG->getMachineNode(Opc2, dl, ResTys, OpsB, 4);
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Chain = SDValue(VLdB, 5);
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SDNode *Q0 = PairDRegs(VT, SDValue(VLdA, 0), SDValue(VLdB, 0));
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SDNode *Q1 = PairDRegs(VT, SDValue(VLdA, 1), SDValue(VLdB, 1));
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SDNode *Q2 = PairDRegs(VT, SDValue(VLdA, 2), SDValue(VLdB, 2));
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SDNode *Q3 = PairDRegs(VT, SDValue(VLdA, 3), SDValue(VLdB, 3));
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ReplaceUses(SDValue(N, 0), SDValue(Q0, 0));
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ReplaceUses(SDValue(N, 1), SDValue(Q1, 0));
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ReplaceUses(SDValue(N, 2), SDValue(Q2, 0));
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ReplaceUses(SDValue(N, 3), SDValue(Q3, 0));
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ReplaceUses(SDValue(N, 4), Chain);
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return NULL;
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unsigned DOpcodes[] = { ARM::VLD4d8, ARM::VLD4d16,
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ARM::VLD4d32, ARM::VLD4d64 };
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unsigned QOpcodes0[] = { ARM::VLD4q8a, ARM::VLD4q16a, ARM::VLD4q32a };
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unsigned QOpcodes1[] = { ARM::VLD4q8b, ARM::VLD4q16b, ARM::VLD4q32b };
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return SelectVLD(Op, 4, DOpcodes, QOpcodes0, QOpcodes1);
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}
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case Intrinsic::arm_neon_vld2lane: {
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