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ARM Cost Model: Modify the target independent cost model to ask

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the target if it supports the different CAST types. We didn't do this
on X86 because of the different register sizes and types, but on ARM
this makes sense.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172245 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nadav Rotem 2013-01-11 19:54:13 +00:00
parent 9c0d0f55da
commit 3e40d927a7
2 changed files with 24 additions and 15 deletions
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33
lib/CodeGen/BasicTargetTransformInfo.cpp
View File

@ -241,6 +241,27 @@ unsigned BasicTTI::getCastInstrCost(unsigned Opcode, Type *Dst,
std::pair<unsigned, MVT> SrcLT = TLI->getTypeLegalizationCost(Src);
std::pair<unsigned, MVT> DstLT = TLI->getTypeLegalizationCost(Dst);
// Check for NOOP conversions.
if (SrcLT.first == DstLT.first &&
SrcLT.second.getSizeInBits() == DstLT.second.getSizeInBits()) {
// Bitcast between types that are legalized to the same type are free.
if (Opcode == Instruction::BitCast || Opcode == Instruction::Trunc)
return 0;
}
if (Opcode == Instruction::Trunc &&
TLI->isTruncateFree(SrcLT.second, DstLT.second))
return 0;
if (Opcode == Instruction::ZExt &&
TLI->isZExtFree(SrcLT.second, DstLT.second))
return 0;
// If the cast is marked as legal (or promote) then assume low cost.
if (TLI->isOperationLegalOrPromote(ISD, DstLT.second))
return 1;
// Handle scalar conversions.
if (!Src->isVectorTy() && !Dst->isVectorTy()) {
@ -248,14 +269,6 @@ unsigned BasicTTI::getCastInstrCost(unsigned Opcode, Type *Dst,
if (Opcode == Instruction::BitCast)
return 0;
if (Opcode == Instruction::Trunc &&
TLI->isTruncateFree(SrcLT.second, DstLT.second))
return 0;
if (Opcode == Instruction::ZExt &&
TLI->isZExtFree(SrcLT.second, DstLT.second))
return 0;
// Just check the op cost. If the operation is legal then assume it costs 1.
if (!TLI->isOperationExpand(ISD, DstLT.second))
return 1;
@ -271,10 +284,6 @@ unsigned BasicTTI::getCastInstrCost(unsigned Opcode, Type *Dst,
if (SrcLT.first == DstLT.first &&
SrcLT.second.getSizeInBits() == DstLT.second.getSizeInBits()) {
// Bitcast between types that are legalized to the same type are free.
if (Opcode == Instruction::BitCast || Opcode == Instruction::Trunc)
return 0;
// Assume that Zext is done using AND.
if (Opcode == Instruction::ZExt)
return 1;

6
test/Transforms/LoopVectorize/ARM/gcc-examples.ll
View File

@ -35,9 +35,9 @@ define void @example1() nounwind uwtable ssp {
}
;CHECK: @example10b
;CHECK: load <2 x i16>
;CHECK: sext <2 x i16>
;CHECK: store <2 x i32>
;CHECK: load <4 x i16>
;CHECK: sext <4 x i16>
;CHECK: store <4 x i32>
;CHECK: ret void
define void @example10b(i16* noalias nocapture %sa, i16* noalias nocapture %sb, i16* noalias nocapture %sc, i32* noalias nocapture %ia, i32* noalias nocapture %ib, i32* noalias nocapture %ic) nounwind uwtable ssp {
br label %1