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Revert "Make NumMicroOps a variable in the subtarget's instruction itinerary."
This reverts commit r159406. I noticed a performance regression so I'll back out for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159411 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -95,7 +95,7 @@ struct InstrStage {
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/// operands are read and written.
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/// operands are read and written.
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///
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///
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struct InstrItinerary {
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struct InstrItinerary {
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int NumMicroOps; ///< # of micro-ops, -1 means it's variable
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unsigned NumMicroOps; ///< # of micro-ops, 0 means it's variable
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unsigned FirstStage; ///< Index of first stage in itinerary
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unsigned FirstStage; ///< Index of first stage in itinerary
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unsigned LastStage; ///< Index of last + 1 stage in itinerary
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unsigned LastStage; ///< Index of last + 1 stage in itinerary
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unsigned FirstOperandCycle; ///< Index of first operand rd/wr
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unsigned FirstOperandCycle; ///< Index of first operand rd/wr
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@ -323,6 +323,7 @@ public:
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}
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}
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};
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};
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} // End llvm namespace
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} // End llvm namespace
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#endif
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#endif
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@ -648,9 +648,7 @@ public:
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}
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}
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/// getNumMicroOps - Return the number of u-operations the given machine
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/// getNumMicroOps - Return the number of u-operations the given machine
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/// instruction will be decoded to on the target cpu. The itinerary's
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/// instruction will be decoded to on the target cpu.
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/// IssueWidth is the number of microops that can be dispatched each
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/// cycle. An instruction with zero microops takes no dispatch resources.
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virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
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virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
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const MachineInstr *MI) const = 0;
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const MachineInstr *MI) const = 0;
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@ -73,20 +73,20 @@ class InstrStage<int cycles, list<FuncUnit> units,
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// across all chip sets. Thus a new chip set can be added without modifying
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// across all chip sets. Thus a new chip set can be added without modifying
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// instruction information.
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// instruction information.
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//
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//
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class InstrItinClass;
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// NumMicroOps represents the number of micro-operations that each instruction
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// in the class are decoded to. If the number is zero, then it means the
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// instruction can decode into variable number of micro-ops and it must be
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// determined dynamically.
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//
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class InstrItinClass<int ops = 1> {
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int NumMicroOps = ops;
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}
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def NoItinerary : InstrItinClass;
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def NoItinerary : InstrItinClass;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction itinerary data - These values provide a runtime map of an
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// Instruction itinerary data - These values provide a runtime map of an
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// instruction itinerary class (name) to its itinerary data.
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// instruction itinerary class (name) to its itinerary data.
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//
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//
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// NumMicroOps represents the number of micro-operations that each instruction
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// in the class are decoded to. If the number is zero, then it means the
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// instruction can decode into variable number of micro-ops and it must be
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// determined dynamically. This directly relates to the itineraries
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// global IssueWidth property, which constrains the number of microops
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// that can issue per cycle.
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//
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// OperandCycles are optional "cycle counts". They specify the cycle after
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// OperandCycles are optional "cycle counts". They specify the cycle after
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// instruction issue the values which correspond to specific operand indices
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// instruction issue the values which correspond to specific operand indices
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// are defined or read. Bypasses are optional "pipeline forwarding pathes", if
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// are defined or read. Bypasses are optional "pipeline forwarding pathes", if
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@ -106,9 +106,8 @@ def NoItinerary : InstrItinClass;
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// is reduced by 1.
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// is reduced by 1.
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class InstrItinData<InstrItinClass Class, list<InstrStage> stages,
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class InstrItinData<InstrItinClass Class, list<InstrStage> stages,
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list<int> operandcycles = [],
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list<int> operandcycles = [],
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list<Bypass> bypasses = [], int uops = 1> {
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list<Bypass> bypasses = []> {
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InstrItinClass TheClass = Class;
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InstrItinClass TheClass = Class;
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int NumMicroOps = uops;
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list<InstrStage> Stages = stages;
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list<InstrStage> Stages = stages;
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list<int> OperandCycles = operandcycles;
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list<int> OperandCycles = operandcycles;
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list<Bypass> Bypasses = bypasses;
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list<Bypass> Bypasses = bypasses;
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@ -560,8 +560,8 @@ TargetInstrInfoImpl::getNumMicroOps(const InstrItineraryData *ItinData,
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return 1;
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return 1;
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unsigned Class = MI->getDesc().getSchedClass();
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unsigned Class = MI->getDesc().getSchedClass();
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int UOps = ItinData->Itineraries[Class].NumMicroOps;
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unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
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if (UOps >= 0)
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if (UOps)
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return UOps;
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return UOps;
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// The # of u-ops is dynamically determined. The specific target should
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// The # of u-ops is dynamically determined. The specific target should
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@ -2176,9 +2176,9 @@ ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
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const MCInstrDesc &Desc = MI->getDesc();
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const MCInstrDesc &Desc = MI->getDesc();
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unsigned Class = Desc.getSchedClass();
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unsigned Class = Desc.getSchedClass();
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int ItinUOps = ItinData->Itineraries[Class].NumMicroOps;
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unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
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if (ItinUOps >= 0)
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if (UOps)
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return ItinUOps;
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return UOps;
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unsigned Opc = MI->getOpcode();
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unsigned Opc = MI->getOpcode();
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switch (Opc) {
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switch (Opc) {
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@ -2252,19 +2252,19 @@ ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
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return 2;
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return 2;
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// 4 registers would be issued: 2, 2.
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// 4 registers would be issued: 2, 2.
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// 5 registers would be issued: 2, 2, 1.
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// 5 registers would be issued: 2, 2, 1.
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int A8UOps = (NumRegs / 2);
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UOps = (NumRegs / 2);
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if (NumRegs % 2)
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if (NumRegs % 2)
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++A8UOps;
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++UOps;
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return A8UOps;
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return UOps;
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} else if (Subtarget.isCortexA9()) {
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} else if (Subtarget.isCortexA9()) {
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int A9UOps = (NumRegs / 2);
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UOps = (NumRegs / 2);
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// If there are odd number of registers or if it's not 64-bit aligned,
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// If there are odd number of registers or if it's not 64-bit aligned,
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// then it takes an extra AGU (Address Generation Unit) cycle.
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// then it takes an extra AGU (Address Generation Unit) cycle.
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if ((NumRegs % 2) ||
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if ((NumRegs % 2) ||
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!MI->hasOneMemOperand() ||
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!MI->hasOneMemOperand() ||
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(*MI->memoperands_begin())->getAlignment() < 8)
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(*MI->memoperands_begin())->getAlignment() < 8)
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++A9UOps;
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++UOps;
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return A9UOps;
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return UOps;
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} else {
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} else {
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// Assume the worst.
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// Assume the worst.
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return NumRegs;
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return NumRegs;
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@ -70,11 +70,11 @@ def IIC_iLoad_bh_siu : InstrItinClass;
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def IIC_iLoad_d_i : InstrItinClass;
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def IIC_iLoad_d_i : InstrItinClass;
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def IIC_iLoad_d_r : InstrItinClass;
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def IIC_iLoad_d_r : InstrItinClass;
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def IIC_iLoad_d_ru : InstrItinClass;
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def IIC_iLoad_d_ru : InstrItinClass;
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def IIC_iLoad_m : InstrItinClass;
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def IIC_iLoad_m : InstrItinClass<0>; // micro-coded
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def IIC_iLoad_mu : InstrItinClass;
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def IIC_iLoad_mu : InstrItinClass<0>; // micro-coded
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def IIC_iLoad_mBr : InstrItinClass;
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def IIC_iLoad_mBr : InstrItinClass<0>; // micro-coded
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def IIC_iPop : InstrItinClass;
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def IIC_iPop : InstrItinClass<0>; // micro-coded
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def IIC_iPop_Br : InstrItinClass;
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def IIC_iPop_Br : InstrItinClass<0>; // micro-coded
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def IIC_iLoadiALU : InstrItinClass;
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def IIC_iLoadiALU : InstrItinClass;
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def IIC_iStore_i : InstrItinClass;
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def IIC_iStore_i : InstrItinClass;
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def IIC_iStore_r : InstrItinClass;
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def IIC_iStore_r : InstrItinClass;
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@ -91,8 +91,8 @@ def IIC_iStore_bh_siu : InstrItinClass;
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def IIC_iStore_d_i : InstrItinClass;
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def IIC_iStore_d_i : InstrItinClass;
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def IIC_iStore_d_r : InstrItinClass;
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def IIC_iStore_d_r : InstrItinClass;
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def IIC_iStore_d_ru : InstrItinClass;
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def IIC_iStore_d_ru : InstrItinClass;
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def IIC_iStore_m : InstrItinClass;
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def IIC_iStore_m : InstrItinClass<0>; // micro-coded
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def IIC_iStore_mu : InstrItinClass;
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def IIC_iStore_mu : InstrItinClass<0>; // micro-coded
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def IIC_Preload : InstrItinClass;
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def IIC_Preload : InstrItinClass;
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def IIC_Br : InstrItinClass;
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def IIC_Br : InstrItinClass;
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def IIC_fpSTAT : InstrItinClass;
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def IIC_fpSTAT : InstrItinClass;
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@ -126,12 +126,12 @@ def IIC_fpSQRT32 : InstrItinClass;
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def IIC_fpSQRT64 : InstrItinClass;
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def IIC_fpSQRT64 : InstrItinClass;
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def IIC_fpLoad32 : InstrItinClass;
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def IIC_fpLoad32 : InstrItinClass;
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def IIC_fpLoad64 : InstrItinClass;
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def IIC_fpLoad64 : InstrItinClass;
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def IIC_fpLoad_m : InstrItinClass;
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def IIC_fpLoad_m : InstrItinClass<0>; // micro-coded
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def IIC_fpLoad_mu : InstrItinClass;
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def IIC_fpLoad_mu : InstrItinClass<0>; // micro-coded
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def IIC_fpStore32 : InstrItinClass;
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def IIC_fpStore32 : InstrItinClass;
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def IIC_fpStore64 : InstrItinClass;
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def IIC_fpStore64 : InstrItinClass;
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def IIC_fpStore_m : InstrItinClass;
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def IIC_fpStore_m : InstrItinClass<0>; // micro-coded
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def IIC_fpStore_mu : InstrItinClass;
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def IIC_fpStore_mu : InstrItinClass<0>; // micro-coded
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def IIC_VLD1 : InstrItinClass;
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def IIC_VLD1 : InstrItinClass;
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def IIC_VLD1x2 : InstrItinClass;
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def IIC_VLD1x2 : InstrItinClass;
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def IIC_VLD1x3 : InstrItinClass;
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def IIC_VLD1x3 : InstrItinClass;
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@ -155,30 +155,28 @@ def CortexA8Itineraries : MultiIssueItineraries<
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// Load multiple, def is the 5th operand. Pipeline 0 only.
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// Load multiple, def is the 5th operand. Pipeline 0 only.
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// FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
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// FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
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InstrItinData<IIC_iLoad_m , [InstrStage<2, [A8_Pipe0], 0>,
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InstrItinData<IIC_iLoad_m , [InstrStage<2, [A8_Pipe0], 0>,
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InstrStage<2, [A8_LSPipe]>],
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InstrStage<2, [A8_LSPipe]>], [1, 1, 1, 1, 3]>,
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[1, 1, 1, 1, 3], [], -1>, // dynamic uops
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//
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//
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// Load multiple + update, defs are the 1st and 5th operands.
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// Load multiple + update, defs are the 1st and 5th operands.
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InstrItinData<IIC_iLoad_mu , [InstrStage<3, [A8_Pipe0], 0>,
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InstrItinData<IIC_iLoad_mu , [InstrStage<3, [A8_Pipe0], 0>,
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InstrStage<3, [A8_LSPipe]>],
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InstrStage<3, [A8_LSPipe]>], [2, 1, 1, 1, 3]>,
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[2, 1, 1, 1, 3], [], -1>, // dynamic uops
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//
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//
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// Load multiple plus branch
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// Load multiple plus branch
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InstrItinData<IIC_iLoad_mBr, [InstrStage<3, [A8_Pipe0], 0>,
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InstrItinData<IIC_iLoad_mBr, [InstrStage<3, [A8_Pipe0], 0>,
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InstrStage<3, [A8_LSPipe]>,
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InstrStage<3, [A8_LSPipe]>,
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InstrStage<1, [A8_Pipe0, A8_Pipe1]>],
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InstrStage<1, [A8_Pipe0, A8_Pipe1]>],
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[1, 2, 1, 1, 3], [], -1>, // dynamic uops
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[1, 2, 1, 1, 3]>,
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//
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//
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// Pop, def is the 3rd operand.
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// Pop, def is the 3rd operand.
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InstrItinData<IIC_iPop , [InstrStage<3, [A8_Pipe0], 0>,
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InstrItinData<IIC_iPop , [InstrStage<3, [A8_Pipe0], 0>,
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InstrStage<3, [A8_LSPipe]>],
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InstrStage<3, [A8_LSPipe]>], [1, 1, 3]>,
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[1, 1, 3], [], -1>, // dynamic uops
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//
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//
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// Push, def is the 3th operand.
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// Push, def is the 3th operand.
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InstrItinData<IIC_iPop_Br, [InstrStage<3, [A8_Pipe0], 0>,
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InstrItinData<IIC_iPop_Br, [InstrStage<3, [A8_Pipe0], 0>,
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InstrStage<3, [A8_LSPipe]>,
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InstrStage<3, [A8_LSPipe]>,
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InstrStage<1, [A8_Pipe0, A8_Pipe1]>],
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InstrStage<1, [A8_Pipe0, A8_Pipe1]>],
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[1, 1, 3], [], -1>, // dynamic uops
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[1, 1, 3]>,
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//
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//
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// iLoadi + iALUr for t2LDRpci_pic.
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// iLoadi + iALUr for t2LDRpci_pic.
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InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
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InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
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@ -233,13 +231,12 @@ def CortexA8Itineraries : MultiIssueItineraries<
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// Store multiple. Pipeline 0 only.
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// Store multiple. Pipeline 0 only.
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// FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
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// FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
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InstrItinData<IIC_iStore_m , [InstrStage<2, [A8_Pipe0], 0>,
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InstrItinData<IIC_iStore_m , [InstrStage<2, [A8_Pipe0], 0>,
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InstrStage<2, [A8_LSPipe]>],
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InstrStage<2, [A8_LSPipe]>]>,
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[], [], -1>, // dynamic uops
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//
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//
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// Store multiple + update
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// Store multiple + update
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InstrItinData<IIC_iStore_mu, [InstrStage<2, [A8_Pipe0], 0>,
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InstrItinData<IIC_iStore_mu, [InstrStage<2, [A8_Pipe0], 0>,
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InstrStage<2, [A8_LSPipe]>],
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InstrStage<2, [A8_LSPipe]>], [2]>,
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[2], [], -1>, // dynamic uops
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//
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//
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// Preload
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// Preload
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InstrItinData<IIC_Preload, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
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InstrItinData<IIC_Preload, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
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@ -400,16 +397,14 @@ def CortexA8Itineraries : MultiIssueItineraries<
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InstrStage<1, [A8_NLSPipe], 0>,
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InstrStage<1, [A8_NLSPipe], 0>,
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InstrStage<1, [A8_LSPipe]>,
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InstrStage<1, [A8_LSPipe]>,
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InstrStage<1, [A8_NLSPipe], 0>,
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InstrStage<1, [A8_NLSPipe], 0>,
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InstrStage<1, [A8_LSPipe]>],
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InstrStage<1, [A8_LSPipe]>], [1, 1, 1, 2]>,
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[1, 1, 1, 2], [], -1>, // dynamic uops
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//
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//
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// FP Load Multiple + update
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// FP Load Multiple + update
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InstrItinData<IIC_fpLoad_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
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InstrItinData<IIC_fpLoad_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
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InstrStage<1, [A8_NLSPipe], 0>,
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InstrStage<1, [A8_NLSPipe], 0>,
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InstrStage<1, [A8_LSPipe]>,
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InstrStage<1, [A8_LSPipe]>,
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InstrStage<1, [A8_NLSPipe], 0>,
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InstrStage<1, [A8_NLSPipe], 0>,
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InstrStage<1, [A8_LSPipe]>],
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InstrStage<1, [A8_LSPipe]>], [2, 1, 1, 1, 2]>,
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[2, 1, 1, 1, 2], [], -1>, // dynamic uops
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//
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//
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// Single-precision FP Store
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// Single-precision FP Store
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InstrItinData<IIC_fpStore32,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
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InstrItinData<IIC_fpStore32,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
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@ -428,16 +423,15 @@ def CortexA8Itineraries : MultiIssueItineraries<
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InstrStage<1, [A8_NLSPipe], 0>,
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InstrStage<1, [A8_NLSPipe], 0>,
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InstrStage<1, [A8_LSPipe]>,
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InstrStage<1, [A8_LSPipe]>,
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InstrStage<1, [A8_NLSPipe], 0>,
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InstrStage<1, [A8_NLSPipe], 0>,
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InstrStage<1, [A8_LSPipe]>],
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InstrStage<1, [A8_LSPipe]>], [1, 1, 1, 1]>,
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[1, 1, 1, 1], [], -1>, // dynamic uops
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//
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//
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// FP Store Multiple + update
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// FP Store Multiple + update
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InstrItinData<IIC_fpStore_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
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InstrItinData<IIC_fpStore_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
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InstrStage<1, [A8_NLSPipe], 0>,
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InstrStage<1, [A8_NLSPipe], 0>,
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InstrStage<1, [A8_LSPipe]>,
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InstrStage<1, [A8_LSPipe]>,
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InstrStage<1, [A8_NLSPipe], 0>,
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InstrStage<1, [A8_NLSPipe], 0>,
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InstrStage<1, [A8_LSPipe]>],
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InstrStage<1, [A8_LSPipe]>], [2, 1, 1, 1, 1]>,
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[2, 1, 1, 1, 1], [], -1>, // dynamic uops
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// NEON
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// NEON
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// Issue through integer pipeline, and execute in NEON unit.
|
// Issue through integer pipeline, and execute in NEON unit.
|
||||||
//
|
//
|
||||||
|
@ -284,8 +284,7 @@ def CortexA9Itineraries : MultiIssueItineraries<
|
|||||||
InstrStage<2, [A9_AGU], 1>,
|
InstrStage<2, [A9_AGU], 1>,
|
||||||
InstrStage<2, [A9_LSUnit]>],
|
InstrStage<2, [A9_LSUnit]>],
|
||||||
[1, 1, 1, 1, 3],
|
[1, 1, 1, 1, 3],
|
||||||
[NoBypass, NoBypass, NoBypass, NoBypass, A9_LdBypass],
|
[NoBypass, NoBypass, NoBypass, NoBypass, A9_LdBypass]>,
|
||||||
-1>, // dynamic uops
|
|
||||||
//
|
//
|
||||||
// Load multiple + update, defs are the 1st and 5th operands.
|
// Load multiple + update, defs are the 1st and 5th operands.
|
||||||
InstrItinData<IIC_iLoad_mu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
InstrItinData<IIC_iLoad_mu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||||
@ -293,8 +292,7 @@ def CortexA9Itineraries : MultiIssueItineraries<
|
|||||||
InstrStage<2, [A9_AGU], 1>,
|
InstrStage<2, [A9_AGU], 1>,
|
||||||
InstrStage<2, [A9_LSUnit]>],
|
InstrStage<2, [A9_LSUnit]>],
|
||||||
[2, 1, 1, 1, 3],
|
[2, 1, 1, 1, 3],
|
||||||
[NoBypass, NoBypass, NoBypass, NoBypass, A9_LdBypass],
|
[NoBypass, NoBypass, NoBypass, NoBypass, A9_LdBypass]>,
|
||||||
-1>, // dynamic uops
|
|
||||||
//
|
//
|
||||||
// Load multiple plus branch
|
// Load multiple plus branch
|
||||||
InstrItinData<IIC_iLoad_mBr, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
InstrItinData<IIC_iLoad_mBr, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||||
@ -303,8 +301,7 @@ def CortexA9Itineraries : MultiIssueItineraries<
|
|||||||
InstrStage<2, [A9_LSUnit]>,
|
InstrStage<2, [A9_LSUnit]>,
|
||||||
InstrStage<1, [A9_Branch]>],
|
InstrStage<1, [A9_Branch]>],
|
||||||
[1, 2, 1, 1, 3],
|
[1, 2, 1, 1, 3],
|
||||||
[NoBypass, NoBypass, NoBypass, NoBypass, A9_LdBypass],
|
[NoBypass, NoBypass, NoBypass, NoBypass, A9_LdBypass]>,
|
||||||
-1>, // dynamic uops
|
|
||||||
//
|
//
|
||||||
// Pop, def is the 3rd operand.
|
// Pop, def is the 3rd operand.
|
||||||
InstrItinData<IIC_iPop , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
InstrItinData<IIC_iPop , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||||
@ -312,8 +309,7 @@ def CortexA9Itineraries : MultiIssueItineraries<
|
|||||||
InstrStage<2, [A9_AGU], 1>,
|
InstrStage<2, [A9_AGU], 1>,
|
||||||
InstrStage<2, [A9_LSUnit]>],
|
InstrStage<2, [A9_LSUnit]>],
|
||||||
[1, 1, 3],
|
[1, 1, 3],
|
||||||
[NoBypass, NoBypass, A9_LdBypass],
|
[NoBypass, NoBypass, A9_LdBypass]>,
|
||||||
-1>, // dynamic uops
|
|
||||||
//
|
//
|
||||||
// Pop + branch, def is the 3rd operand.
|
// Pop + branch, def is the 3rd operand.
|
||||||
InstrItinData<IIC_iPop_Br, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
InstrItinData<IIC_iPop_Br, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||||
@ -322,8 +318,8 @@ def CortexA9Itineraries : MultiIssueItineraries<
|
|||||||
InstrStage<2, [A9_LSUnit]>,
|
InstrStage<2, [A9_LSUnit]>,
|
||||||
InstrStage<1, [A9_Branch]>],
|
InstrStage<1, [A9_Branch]>],
|
||||||
[1, 1, 3],
|
[1, 1, 3],
|
||||||
[NoBypass, NoBypass, A9_LdBypass],
|
[NoBypass, NoBypass, A9_LdBypass]>,
|
||||||
-1>, // dynamic uops
|
|
||||||
//
|
//
|
||||||
// iLoadi + iALUr for t2LDRpci_pic.
|
// iLoadi + iALUr for t2LDRpci_pic.
|
||||||
InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||||
@ -417,15 +413,14 @@ def CortexA9Itineraries : MultiIssueItineraries<
|
|||||||
InstrItinData<IIC_iStore_m , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
InstrItinData<IIC_iStore_m , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||||
InstrStage<1, [A9_MUX0], 0>,
|
InstrStage<1, [A9_MUX0], 0>,
|
||||||
InstrStage<1, [A9_AGU], 0>,
|
InstrStage<1, [A9_AGU], 0>,
|
||||||
InstrStage<2, [A9_LSUnit]>],
|
InstrStage<2, [A9_LSUnit]>]>,
|
||||||
[], [], -1>, // dynamic uops
|
|
||||||
//
|
//
|
||||||
// Store multiple + update
|
// Store multiple + update
|
||||||
InstrItinData<IIC_iStore_mu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
InstrItinData<IIC_iStore_mu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||||
InstrStage<1, [A9_MUX0], 0>,
|
InstrStage<1, [A9_MUX0], 0>,
|
||||||
InstrStage<1, [A9_AGU], 0>,
|
InstrStage<1, [A9_AGU], 0>,
|
||||||
InstrStage<2, [A9_LSUnit]>],
|
InstrStage<2, [A9_LSUnit]>], [2]>,
|
||||||
[2], [], -1>, // dynamic uops
|
|
||||||
//
|
//
|
||||||
// Preload
|
// Preload
|
||||||
InstrItinData<IIC_Preload, [InstrStage<1, [A9_Issue0, A9_Issue1]>], [1, 1]>,
|
InstrItinData<IIC_Preload, [InstrStage<1, [A9_Issue0, A9_Issue1]>], [1, 1]>,
|
||||||
@ -722,8 +717,7 @@ def CortexA9Itineraries : MultiIssueItineraries<
|
|||||||
InstrStage<1, [A9_DRegsVFP], 0, Required>,
|
InstrStage<1, [A9_DRegsVFP], 0, Required>,
|
||||||
InstrStage<2, [A9_DRegsN], 0, Reserved>,
|
InstrStage<2, [A9_DRegsN], 0, Reserved>,
|
||||||
InstrStage<1, [A9_NPipe], 0>,
|
InstrStage<1, [A9_NPipe], 0>,
|
||||||
InstrStage<2, [A9_LSUnit]>],
|
InstrStage<2, [A9_LSUnit]>], [1, 1, 1, 1]>,
|
||||||
[1, 1, 1, 1], [], -1>, // dynamic uops
|
|
||||||
//
|
//
|
||||||
// FP Load Multiple + update
|
// FP Load Multiple + update
|
||||||
// FIXME: assumes 2 doubles which requires 2 LS cycles.
|
// FIXME: assumes 2 doubles which requires 2 LS cycles.
|
||||||
@ -732,8 +726,7 @@ def CortexA9Itineraries : MultiIssueItineraries<
|
|||||||
InstrStage<1, [A9_DRegsVFP], 0, Required>,
|
InstrStage<1, [A9_DRegsVFP], 0, Required>,
|
||||||
InstrStage<2, [A9_DRegsN], 0, Reserved>,
|
InstrStage<2, [A9_DRegsN], 0, Reserved>,
|
||||||
InstrStage<1, [A9_NPipe], 0>,
|
InstrStage<1, [A9_NPipe], 0>,
|
||||||
InstrStage<2, [A9_LSUnit]>],
|
InstrStage<2, [A9_LSUnit]>], [2, 1, 1, 1]>,
|
||||||
[2, 1, 1, 1], [], -1>, // dynamic uops
|
|
||||||
//
|
//
|
||||||
// Single-precision FP Store
|
// Single-precision FP Store
|
||||||
InstrItinData<IIC_fpStore32,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
InstrItinData<IIC_fpStore32,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||||
@ -760,8 +753,7 @@ def CortexA9Itineraries : MultiIssueItineraries<
|
|||||||
InstrStage<1, [A9_DRegsVFP], 0, Required>,
|
InstrStage<1, [A9_DRegsVFP], 0, Required>,
|
||||||
InstrStage<2, [A9_DRegsN], 0, Reserved>,
|
InstrStage<2, [A9_DRegsN], 0, Reserved>,
|
||||||
InstrStage<1, [A9_NPipe], 0>,
|
InstrStage<1, [A9_NPipe], 0>,
|
||||||
InstrStage<2, [A9_LSUnit]>],
|
InstrStage<2, [A9_LSUnit]>], [1, 1, 1, 1]>,
|
||||||
[1, 1, 1, 1], [], -1>, // dynamic uops
|
|
||||||
//
|
//
|
||||||
// FP Store Multiple + update
|
// FP Store Multiple + update
|
||||||
// FIXME: assumes 2 doubles which requires 2 LS cycles.
|
// FIXME: assumes 2 doubles which requires 2 LS cycles.
|
||||||
@ -770,8 +762,7 @@ def CortexA9Itineraries : MultiIssueItineraries<
|
|||||||
InstrStage<1, [A9_DRegsVFP], 0, Required>,
|
InstrStage<1, [A9_DRegsVFP], 0, Required>,
|
||||||
InstrStage<2, [A9_DRegsN], 0, Reserved>,
|
InstrStage<2, [A9_DRegsN], 0, Reserved>,
|
||||||
InstrStage<1, [A9_NPipe], 0>,
|
InstrStage<1, [A9_NPipe], 0>,
|
||||||
InstrStage<2, [A9_LSUnit]>],
|
InstrStage<2, [A9_LSUnit]>], [2, 1, 1, 1]>,
|
||||||
[2, 1, 1, 1], [], -1>, // dynamic uops
|
|
||||||
// NEON
|
// NEON
|
||||||
// VLD1
|
// VLD1
|
||||||
InstrItinData<IIC_VLD1, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
InstrItinData<IIC_VLD1, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||||
|
@ -498,7 +498,7 @@ void SubtargetEmitter::EmitStageAndOperandCycleData(raw_ostream &OS,
|
|||||||
unsigned Find = ItinClassesMap[Name];
|
unsigned Find = ItinClassesMap[Name];
|
||||||
|
|
||||||
// Set up itinerary as location and location + stage count
|
// Set up itinerary as location and location + stage count
|
||||||
unsigned NumUOps = ItinData->getValueAsInt("NumMicroOps");
|
unsigned NumUOps = ItinClassList[Find]->getValueAsInt("NumMicroOps");
|
||||||
InstrItinerary Intinerary = { NumUOps, FindStage, FindStage + NStages,
|
InstrItinerary Intinerary = { NumUOps, FindStage, FindStage + NStages,
|
||||||
FindOperandCycle,
|
FindOperandCycle,
|
||||||
FindOperandCycle + NOperandCycles};
|
FindOperandCycle + NOperandCycles};
|
||||||
|
Loading…
Reference in New Issue
Block a user