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[mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double

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precision loads and stores as well as reg+imm double precision loads and stores.

Previously, expansion of loads and stores was done after register allocation,
but now it takes place during legalization. As a result, users will see double
precision stores and loads being emitted to spill and restore 64-bit FP registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190235 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
2013-09-07 00:52:30 +00:00
parent d65d2fde4e
commit 3e6758541b
7 changed files with 147 additions and 89 deletions
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78
test/CodeGen/Mips/mno-ldc1-sdc1.ll
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@@ -1,22 +1,31 @@
; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 < %s | \
; RUN: FileCheck %s -check-prefix=LE-PIC
; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s -check-prefix=LE-PIC
; RUN: llc -march=mipsel -relocation-model=static -mno-ldc1-sdc1 < %s | \
; RUN: FileCheck %s -check-prefix=LE-STATIC
; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 < %s | \
; RUN: FileCheck %s -check-prefix=BE-PIC
; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=CHECK-LDC1-SDC1
; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | \
; RUN: FileCheck %s -check-prefix=CHECK-LDC1-SDC1
@g0 = common global double 0.000000e+00, align 8
; LE-PIC-LABEL: test_ldc1:
; LE-PIC: lwc1 $f0, 0(${{[0-9]+}})
; LE-PIC: lwc1 $f1, 4(${{[0-9]+}})
; LE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
; LE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
; LE-PIC-DAG: mtc1 $[[R0]], $f0
; LE-PIC-DAG: mtc1 $[[R1]], $f1
; LE-STATIC-LABEL: test_ldc1:
; LE-STATIC: lwc1 $f0, %lo(g0)(${{[0-9]+}})
; LE-STATIC: lwc1 $f1, %lo(g0+4)(${{[0-9]+}})
; LE-STATIC-DAG: lui $[[R0:[0-9]+]], %hi(g0)
; LE-STATIC-DAG: lw $[[R1:[0-9]+]], %lo(g0)($[[R0]])
; LE-STATIC-DAG: addiu $[[R2:[0-9]+]], $[[R0]], %lo(g0)
; LE-STATIC-DAG: lw $[[R3:[0-9]+]], 4($[[R2]])
; LE-STATIC-DAG: mtc1 $[[R1]], $f0
; LE-STATIC-DAG: mtc1 $[[R3]], $f1
; BE-PIC-LABEL: test_ldc1:
; BE-PIC: lwc1 $f1, 0(${{[0-9]+}})
; BE-PIC: lwc1 $f0, 4(${{[0-9]+}})
; BE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
; BE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
; BE-PIC-DAG: mtc1 $[[R1]], $f0
; BE-PIC-DAG: mtc1 $[[R0]], $f1
; CHECK-LDC1-SDC1-LABEL: test_ldc1:
; CHECK-LDC1-SDC1: ldc1 $f{{[0-9]+}}
@@ -27,14 +36,22 @@ entry:
}
; LE-PIC-LABEL: test_sdc1:
; LE-PIC: swc1 $f12, 0(${{[0-9]+}})
; LE-PIC: swc1 $f13, 4(${{[0-9]+}})
; LE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
; LE-PIC-DAG: mfc1 $[[R1:[0-9]+]], $f13
; LE-PIC-DAG: sw $[[R0]], 0(${{[0-9]+}})
; LE-PIC-DAG: sw $[[R1]], 4(${{[0-9]+}})
; LE-STATIC-LABEL: test_sdc1:
; LE-STATIC: swc1 $f12, %lo(g0)(${{[0-9]+}})
; LE-STATIC: swc1 $f13, %lo(g0+4)(${{[0-9]+}})
; LE-STATIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
; LE-STATIC-DAG: mfc1 $[[R1:[0-9]+]], $f13
; LE-STATIC-DAG: lui $[[R2:[0-9]+]], %hi(g0)
; LE-STATIC-DAG: sw $[[R0]], %lo(g0)($[[R2]])
; LE-STATIC-DAG: addiu $[[R3:[0-9]+]], $[[R2]], %lo(g0)
; LE-STATIC-DAG: sw $[[R1]], 4($[[R3]])
; BE-PIC-LABEL: test_sdc1:
; BE-PIC: swc1 $f13, 0(${{[0-9]+}})
; BE-PIC: swc1 $f12, 4(${{[0-9]+}})
; BE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
; BE-PIC-DAG: mfc1 $[[R1:[0-9]+]], $f13
; BE-PIC-DAG: sw $[[R1]], 0(${{[0-9]+}})
; BE-PIC-DAG: sw $[[R0]], 4(${{[0-9]+}})
; CHECK-LDC1-SDC1-LABEL: test_sdc1:
; CHECK-LDC1-SDC1: sdc1 $f{{[0-9]+}}
@@ -43,3 +60,34 @@ entry:
store double %a, double* @g0, align 8
ret void
}
; CHECK-LE-PIC-DAG-LABEL: test_ldxc1:
; LE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
; LE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
; LE-PIC-DAG: mtc1 $[[R0]], $f0
; LE-PIC-DAG: mtc1 $[[R1]], $f1
; CHECK-LDC1-SDC1-LABEL: test_ldxc1:
; CHECK-LDC1-SDC1: ldxc1 $f{{[0-9]+}}
define double @test_ldxc1(double* nocapture readonly %a, i32 %i) {
entry:
%arrayidx = getelementptr inbounds double* %a, i32 %i
%0 = load double* %arrayidx, align 8
ret double %0
}
; LE-PIC-DAG-LABEL: test_sdxc1:
; LE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
; LE-PIC-DAG: mfc1 $[[R1:[0-9]+]], $f13
; LE-PIC-DAG: sw $[[R0]], 0(${{[0-9]+}})
; LE-PIC-DAG: sw $[[R1]], 4(${{[0-9]+}})
; CHECK-LDC1-SDC1-LABEL: test_sdxc1:
; CHECK-LDC1-SDC1: sdxc1 $f{{[0-9]+}}
define void @test_sdxc1(double %b, double* nocapture %a, i32 %i) {
entry:
%arrayidx = getelementptr inbounds double* %a, i32 %i
store double %b, double* %arrayidx, align 8
ret void
}