mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2026-04-21 23:17:16 +00:00
initial fp support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19847 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth
@@ -53,6 +53,14 @@ namespace {
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setOperationAction(ISD::ZERO_EXTEND_INREG, MVT::i1, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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// setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
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// setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
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setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
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setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
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setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
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setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
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setOperationAction(ISD::FP_TO_SINT , MVT::f32 , Promote);
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computeRegisterProperties();
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@@ -124,18 +132,35 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
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//Handle the return address
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//BuildMI(&BB, Alpha::IDEF, 0, Alpha::R26);
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unsigned args[] = {Alpha::R16, Alpha::R17, Alpha::R18,
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Alpha::R19, Alpha::R20, Alpha::R21};
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unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
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Alpha::R19, Alpha::R20, Alpha::R21};
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unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
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Alpha::F19, Alpha::F20, Alpha::F21};
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std::vector<unsigned> argVreg;
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std::vector<unsigned> argPreg;
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int count = 0;
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for (Function::aiterator I = F.abegin(), E = F.aend(); I != E; ++I)
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{
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++count;
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assert(count <= 6 && "More than 6 args not supported");
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assert(getValueType(I->getType()) != MVT::f64 && "No floats yet");
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BuildMI(&BB, Alpha::IDEF, 0, args[count - 1]);
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argVreg.push_back(MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64)));
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switch (getValueType(I->getType())) {
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default: std::cerr << "Unknown Type " << getValueType(I->getType()) << "\n"; abort();
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case MVT::f64:
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case MVT::f32:
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BuildMI(&BB, Alpha::IDEF, 0, args_float[count - 1]);
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argVreg.push_back(MF.getSSARegMap()->createVirtualRegister(getRegClassFor(getValueType(I->getType()))));
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argPreg.push_back(args_float[count - 1]);
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break;
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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case MVT::i64:
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BuildMI(&BB, Alpha::IDEF, 0, args_int[count - 1]);
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argVreg.push_back(MF.getSSARegMap()->createVirtualRegister(getRegClassFor(getValueType(I->getType()))));
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argPreg.push_back(args_int[count - 1]);
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break;
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}
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}
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BuildMI(&BB, Alpha::IDEF, 0, Alpha::R29);
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@@ -143,25 +168,30 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
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count = 0;
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for (Function::aiterator I = F.abegin(), E = F.aend(); I != E; ++I)
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{
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BuildMI(&BB, Alpha::BIS, 2, argVreg[count]).addReg(args[count]).addReg(args[count]);
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SDOperand argt, newroot;
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SDOperand newroot;
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unsigned Opc;
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switch (getValueType(I->getType()))
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{
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default: assert(0 && "Unhandled type");
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case MVT::i64:
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argt = newroot = DAG.getCopyFromReg(argVreg[count], MVT::i64, DAG.getRoot());
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break;
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case MVT::i32:
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argt = newroot = DAG.getCopyFromReg(argVreg[count], MVT::i32, DAG.getRoot());
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case MVT::i16:
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case MVT::i8:
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case MVT::i1:
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Opc = Alpha::BIS;
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break;
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case MVT::f32:
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case MVT::f64:
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Opc = Alpha::CPYS;
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break;
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default:
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newroot = DAG.getCopyFromReg(argVreg[count], MVT::i64, DAG.getRoot());
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argt = DAG.getNode(ISD::TRUNCATE, getValueType(I->getType()), newroot);
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}
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BuildMI(&BB, Opc, 2, argVreg[count]).addReg(argPreg[count]).addReg(argPreg[count]);
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newroot = DAG.getCopyFromReg(argVreg[count], getValueType(I->getType()), DAG.getRoot());
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DAG.setRoot(newroot.getValue(1));
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ArgValues.push_back(argt);
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ArgValues.push_back(newroot);
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++count;
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}
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return ArgValues;
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}
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@@ -184,9 +214,9 @@ AlphaTargetLowering::LowerCallTo(SDOperand Chain,
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// Promote the integer to 64 bits. If the input type is signed use a
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// sign extend, otherwise use a zero extend.
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if (Args[i].second->isSigned())
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Args[i].first = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].first);
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Args[i].first = DAG.getNode(ISD::SIGN_EXTEND_INREG, MVT::i64, Args[i].first);
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else
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Args[i].first = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].first);
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Args[i].first = DAG.getNode(ISD::ZERO_EXTEND_INREG, MVT::i64, Args[i].first);
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break;
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case MVT::i64:
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break;
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@@ -317,18 +347,12 @@ unsigned ISel::SelectExpr(SDOperand N) {
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Tmp1 = SelectExpr(Node->getOperand(1));
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switch(Node->getValueType(0)) {
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default: assert(0 && "Unknown type to sign extend to.");
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default: Node->dump(); assert(0 && "Unknown type to sign extend to.");
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case MVT::i64:
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switch (cast<MVTSDNode>(Node)->getExtraValueType()) {
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default:
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std::cerr << cast<MVTSDNode>(Node)->getExtraValueType()
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<< "(i1 is " << MVT::i1
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<< " i8 is " << MVT::i8
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<< " i16 is " << MVT::i16
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<< " i32 is " << MVT::i32
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<< " i64 is " << MVT::i64
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<< ")\n";
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assert(0 && "Bad extend load!");
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Node->dump();
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assert(0 && "Bad extend load!");
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case MVT::i64:
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BuildMI(BB, Alpha::LDQ, 2, Result).addImm(0).addReg(Tmp1);
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break;
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@@ -357,11 +381,12 @@ unsigned ISel::SelectExpr(SDOperand N) {
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Select(Node->getOperand(0)); // chain
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Tmp1 = SelectExpr(Node->getOperand(1));
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switch(Node->getValueType(0)) {
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default: assert(0 && "Unknown type to sign extend to.");
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default: Node->dump(); assert(0 && "Unknown type to sign extend to.");
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case MVT::i64:
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switch (cast<MVTSDNode>(Node)->getExtraValueType()) {
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default:
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assert(0 && "Bad sign extend!");
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Node->dump();
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assert(0 && "Bad sign extend!");
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case MVT::i32:
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BuildMI(BB, Alpha::LDL, 2, Result).addImm(0).addReg(Tmp1);
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break;
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@@ -386,11 +411,12 @@ unsigned ISel::SelectExpr(SDOperand N) {
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Select(Node->getOperand(0)); // chain
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Tmp1 = SelectExpr(Node->getOperand(1));
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switch(Node->getValueType(0)) {
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default: assert(0 && "Unknown type to zero extend to.");
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default: Node->dump(); assert(0 && "Unknown type to zero extend to.");
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case MVT::i64:
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switch (cast<MVTSDNode>(Node)->getExtraValueType()) {
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default:
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assert(0 && "Bad sign extend!");
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Node->dump();
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assert(0 && "Bad sign extend!");
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case MVT::i16:
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BuildMI(BB, Alpha::LDWU, 2, Result).addImm(0).addReg(Tmp1);
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break;
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@@ -412,7 +438,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
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case ISD::CALL:
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{
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Select(N.getOperand(0));
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// The chain for this call is now lowered.
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ExprMap.insert(std::make_pair(N.getValue(Node->getNumValues()-1), 1));
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@@ -420,67 +446,86 @@ unsigned ISel::SelectExpr(SDOperand N) {
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std::vector<unsigned> argvregs;
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assert(Node->getNumOperands() < 8 && "Only 6 args supported");
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for(int i = 2, e = Node->getNumOperands(); i < e; ++i)
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{
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argvregs.push_back(SelectExpr(N.getOperand(i)));
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}
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argvregs.push_back(SelectExpr(N.getOperand(i)));
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for(int i = 0, e = argvregs.size(); i < e; ++i)
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{
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unsigned args[] = {Alpha::R16, Alpha::R17, Alpha::R18,
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Alpha::R19, Alpha::R20, Alpha::R21};
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BuildMI(BB, Alpha::BIS, 2, args[i]).addReg(argvregs[i]).addReg(argvregs[i]);
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{
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unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
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Alpha::R19, Alpha::R20, Alpha::R21};
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unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
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Alpha::F19, Alpha::F20, Alpha::F21};
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switch(N.getOperand(i).getValueType()) {
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default: Node->dump(); assert(0 && "Unknown value type for call");
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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case MVT::i64:
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BuildMI(BB, Alpha::BIS, 2, args_int[i]).addReg(argvregs[i]).addReg(argvregs[i]);
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break;
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case MVT::f32:
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case MVT::f64:
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BuildMI(BB, Alpha::CPYS, 2, args_float[i]).addReg(argvregs[i]).addReg(argvregs[i]);
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break;
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}
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}
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//build the right kind of call
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if (GlobalAddressSDNode *GASD =
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dyn_cast<GlobalAddressSDNode>(N.getOperand(1)))
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{
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Select(N.getOperand(0));
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AlphaLowering.restoreGP(BB);
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BuildMI(BB, Alpha::CALL, 1).addGlobalAddress(GASD->getGlobal(),true);
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}
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else if (ExternalSymbolSDNode *ESSDN =
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dyn_cast<ExternalSymbolSDNode>(N.getOperand(1)))
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{
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Select(N.getOperand(0));
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AlphaLowering.restoreGP(BB);
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BuildMI(BB, Alpha::CALL, 0).addExternalSymbol(ESSDN->getSymbol(), true);
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}
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else
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{
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Select(N.getOperand(0));
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Tmp1 = SelectExpr(N.getOperand(1));
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BuildMI(BB, Alpha::CALL, 1).addReg(Tmp1);
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AlphaLowering.restoreGP(BB);
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}
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//push the result into a virtual register
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// if (Result != 1)
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// BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R0).addReg(Alpha::R0);
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switch (Node->getValueType(0)) {
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default: Node->dump(); assert(0 && "Unknown value type for call result!");
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case MVT::Other: return 1;
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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case MVT::i64:
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BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R0).addReg(Alpha::R0);
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break;
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case MVT::f32:
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case MVT::f64:
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BuildMI(BB, Alpha::CPYS, 2, Result).addReg(Alpha::F0).addReg(Alpha::F0);
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break;
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}
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//build the right kind of call
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if (GlobalAddressSDNode *GASD =
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dyn_cast<GlobalAddressSDNode>(N.getOperand(1)))
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{
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Select(N.getOperand(0));
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AlphaLowering.restoreGP(BB);
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BuildMI(BB, Alpha::CALL, 1).addGlobalAddress(GASD->getGlobal(),true);
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}
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else if (ExternalSymbolSDNode *ESSDN =
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dyn_cast<ExternalSymbolSDNode>(N.getOperand(1)))
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{
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Select(N.getOperand(0));
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AlphaLowering.restoreGP(BB);
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BuildMI(BB, Alpha::CALL, 0).addExternalSymbol(ESSDN->getSymbol(), true);
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}
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else {
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Select(N.getOperand(0));
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Tmp1 = SelectExpr(N.getOperand(1));
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BuildMI(BB, Alpha::CALL, 1).addReg(Tmp1);
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AlphaLowering.restoreGP(BB);
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}
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//push the result into a virtual register
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// if (Result != 1)
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// BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R0).addReg(Alpha::R0);
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switch (Node->getValueType(0)) {
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default: assert(0 && "Unknown value type for call result!");
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case MVT::Other: return 1;
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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case MVT::i64:
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BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R0).addReg(Alpha::R0);
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break;
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}
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return Result+N.ResNo;
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return Result+N.ResNo;
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}
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case ISD::SIGN_EXTEND:
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case ISD::SIGN_EXTEND_INREG:
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{
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Tmp1 = SelectExpr(N.getOperand(0));
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MVTSDNode* MVN = dyn_cast<MVTSDNode>(Node);
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std::cerr << "SrcT: " << MVN->getExtraValueType() << "\n";
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//std::cerr << "SrcT: " << MVN->getExtraValueType() << "\n";
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switch(MVN->getExtraValueType())
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{
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default:
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assert(0 && "Sign Extend InReg not there yet");
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Node->dump();
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assert(0 && "Sign Extend InReg not there yet");
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break;
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case MVT::i32:
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{
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@@ -500,11 +545,12 @@ unsigned ISel::SelectExpr(SDOperand N) {
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{
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Tmp1 = SelectExpr(N.getOperand(0));
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MVTSDNode* MVN = dyn_cast<MVTSDNode>(Node);
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std::cerr << "SrcT: " << MVN->getExtraValueType() << "\n";
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//std::cerr << "SrcT: " << MVN->getExtraValueType() << "\n";
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switch(MVN->getExtraValueType())
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{
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default:
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assert(0 && "Zero Extend InReg not there yet");
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Node->dump();
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assert(0 && "Zero Extend InReg not there yet");
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break;
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case MVT::i32: Tmp2 = 0xf0; break;
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case MVT::i16: Tmp2 = 0xfc; break;
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@@ -520,7 +566,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
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if (SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(Node)) {
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if (MVT::isInteger(SetCC->getOperand(0).getValueType())) {
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switch (SetCC->getCondition()) {
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default: assert(0 && "Unknown integer comparison!");
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default: Node->dump(); assert(0 && "Unknown integer comparison!");
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case ISD::SETEQ:
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BuildMI(BB, Alpha::CMPEQ, 2, Result).addReg(Tmp1).addReg(Tmp2);
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break;
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@@ -558,11 +604,16 @@ unsigned ISel::SelectExpr(SDOperand N) {
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}
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}
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else
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assert(0 && "only integer");
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{
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Node->dump();
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assert(0 && "only integer");
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}
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}
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else
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assert(0 && "Not a setcc in setcc");
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{
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Node->dump();
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assert(0 && "Not a setcc in setcc");
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}
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return Result;
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case ISD::CopyFromReg:
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@@ -587,94 +638,159 @@ unsigned ISel::SelectExpr(SDOperand N) {
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case ISD::SHL:
|
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case ISD::SRL:
|
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case ISD::MUL:
|
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if(N.getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(1))->getValue() >= 0 &&
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cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255)
|
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{
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switch(N.getOpcode()) {
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case ISD::AND: Opc = Alpha::ANDi; break;
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case ISD::OR: Opc = Alpha::BISi; break;
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case ISD::XOR: Opc = Alpha::XORi; break;
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case ISD::SHL: Opc = Alpha::SLi; break;
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case ISD::SRL: Opc = Alpha::SRLi; break;
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case ISD::SRA: Opc = Alpha::SRAi; break;
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case ISD::MUL: Opc = Alpha::MULQi; break;
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};
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
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}
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else
|
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{
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switch(N.getOpcode()) {
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case ISD::AND: Opc = Alpha::AND; break;
|
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case ISD::OR: Opc = Alpha::BIS; break;
|
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case ISD::XOR: Opc = Alpha::XOR; break;
|
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case ISD::SHL: Opc = Alpha::SL; break;
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case ISD::SRL: Opc = Alpha::SRL; break;
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case ISD::SRA: Opc = Alpha::SRA; break;
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case ISD::MUL: Opc = Alpha::MULQ; break;
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};
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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}
|
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switch (N.getValueType()) {
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default: Node->dump(); assert (0 && "unhandled type");
|
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case MVT::f64:
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assert(N.getOpcode() == ISD::MUL && "only mul here please");
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, Alpha::MULT, 2, Result).addReg(Tmp1).addReg(Tmp2);
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break;
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case MVT::f32:
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assert(N.getOpcode() == ISD::MUL && "only mul here please");
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Tmp1 = SelectExpr(N.getOperand(0));
|
||||
Tmp2 = SelectExpr(N.getOperand(1));
|
||||
BuildMI(BB, Alpha::MULS, 2, Result).addReg(Tmp1).addReg(Tmp2);
|
||||
break;
|
||||
case MVT::i64:
|
||||
if(N.getOperand(1).getOpcode() == ISD::Constant &&
|
||||
cast<ConstantSDNode>(N.getOperand(1))->getValue() >= 0 &&
|
||||
cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255)
|
||||
{
|
||||
switch(N.getOpcode()) {
|
||||
case ISD::AND: Opc = Alpha::ANDi; break;
|
||||
case ISD::OR: Opc = Alpha::BISi; break;
|
||||
case ISD::XOR: Opc = Alpha::XORi; break;
|
||||
case ISD::SHL: Opc = Alpha::SLi; break;
|
||||
case ISD::SRL: Opc = Alpha::SRLi; break;
|
||||
case ISD::SRA: Opc = Alpha::SRAi; break;
|
||||
case ISD::MUL: Opc = Alpha::MULQi; break;
|
||||
};
|
||||
Tmp1 = SelectExpr(N.getOperand(0));
|
||||
Tmp2 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
|
||||
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
|
||||
}
|
||||
else
|
||||
{
|
||||
switch(N.getOpcode()) {
|
||||
case ISD::AND: Opc = Alpha::AND; break;
|
||||
case ISD::OR: Opc = Alpha::BIS; break;
|
||||
case ISD::XOR: Opc = Alpha::XOR; break;
|
||||
case ISD::SHL: Opc = Alpha::SL; break;
|
||||
case ISD::SRL: Opc = Alpha::SRL; break;
|
||||
case ISD::SRA: Opc = Alpha::SRA; break;
|
||||
case ISD::MUL: Opc = Alpha::MULQ; break;
|
||||
};
|
||||
Tmp1 = SelectExpr(N.getOperand(0));
|
||||
Tmp2 = SelectExpr(N.getOperand(1));
|
||||
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
|
||||
}
|
||||
break;
|
||||
}
|
||||
return Result;
|
||||
|
||||
case ISD::ADD:
|
||||
case ISD::SUB:
|
||||
{
|
||||
bool isAdd = N.getOpcode() == ISD::ADD;
|
||||
|
||||
//FIXME: first check for Scaled Adds and Subs!
|
||||
if(N.getOperand(1).getOpcode() == ISD::Constant &&
|
||||
cast<ConstantSDNode>(N.getOperand(1))->getValue() >= 0 &&
|
||||
cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255)
|
||||
{ //Normal imm add/sub
|
||||
Opc = isAdd ? Alpha::ADDQi : Alpha::SUBQi;
|
||||
Tmp1 = SelectExpr(N.getOperand(0));
|
||||
Tmp2 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
|
||||
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
|
||||
}
|
||||
else if(N.getOperand(1).getOpcode() == ISD::Constant &&
|
||||
cast<ConstantSDNode>(N.getOperand(1))->getValue() >= 0 &&
|
||||
cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 32767)
|
||||
{ //LDA //FIXME: expand the above condition a bit
|
||||
Tmp1 = SelectExpr(N.getOperand(0));
|
||||
Tmp2 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
|
||||
if (!isAdd)
|
||||
Tmp2 = -Tmp2;
|
||||
BuildMI(BB, Alpha::LDA, 2, Result).addImm(Tmp2).addReg(Tmp1);
|
||||
}
|
||||
else
|
||||
{ //Normal add/sub
|
||||
Opc = isAdd ? Alpha::ADDQ : Alpha::SUBQ;
|
||||
Tmp1 = SelectExpr(N.getOperand(0));
|
||||
Tmp2 = SelectExpr(N.getOperand(1));
|
||||
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
|
||||
|
||||
}
|
||||
return Result;
|
||||
|
||||
switch (N.getValueType()) {
|
||||
default: Node->dump(); assert(0 && "Unhandled type");
|
||||
case MVT::i64: {
|
||||
//FIXME: first check for Scaled Adds and Subs!
|
||||
if(N.getOperand(1).getOpcode() == ISD::Constant &&
|
||||
cast<ConstantSDNode>(N.getOperand(1))->getValue() >= 0 &&
|
||||
cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255)
|
||||
{ //Normal imm add/sub
|
||||
Opc = isAdd ? Alpha::ADDQi : Alpha::SUBQi;
|
||||
Tmp1 = SelectExpr(N.getOperand(0));
|
||||
Tmp2 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
|
||||
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
|
||||
}
|
||||
else if(N.getOperand(1).getOpcode() == ISD::Constant &&
|
||||
cast<ConstantSDNode>(N.getOperand(1))->getValue() >= 0 &&
|
||||
cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 32767)
|
||||
{ //LDA //FIXME: expand the above condition a bit
|
||||
Tmp1 = SelectExpr(N.getOperand(0));
|
||||
Tmp2 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
|
||||
if (!isAdd)
|
||||
Tmp2 = -Tmp2;
|
||||
BuildMI(BB, Alpha::LDA, 2, Result).addImm(Tmp2).addReg(Tmp1);
|
||||
}
|
||||
else
|
||||
{ //Normal add/sub
|
||||
Opc = isAdd ? Alpha::ADDQ : Alpha::SUBQ;
|
||||
Tmp1 = SelectExpr(N.getOperand(0));
|
||||
Tmp2 = SelectExpr(N.getOperand(1));
|
||||
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
|
||||
}
|
||||
} break;
|
||||
case MVT::f64:
|
||||
case MVT::f32:
|
||||
if (N.getValueType() == MVT::f64)
|
||||
Opc = isAdd ? Alpha::ADDT : Alpha::SUBT;
|
||||
else
|
||||
Opc = isAdd ? Alpha::ADDS : Alpha::SUBS;
|
||||
//
|
||||
Tmp1 = SelectExpr(N.getOperand(0));
|
||||
Tmp2 = SelectExpr(N.getOperand(1));
|
||||
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
|
||||
break;
|
||||
}
|
||||
return Result;
|
||||
}
|
||||
|
||||
case ISD::UREM:
|
||||
case ISD::SREM:
|
||||
case ISD::SDIV:
|
||||
case ISD::UDIV:
|
||||
//FIXME: alpha really doesn't support any of these operations,
|
||||
// the ops are expanded into special library calls with
|
||||
// special calling conventions
|
||||
switch(N.getOpcode()) {
|
||||
case ISD::UREM: Opc = Alpha::REMQU; break;
|
||||
case ISD::SREM: Opc = Alpha::REMQ; break;
|
||||
case ISD::UDIV: Opc = Alpha::DIVQU; break;
|
||||
case ISD::SDIV: Opc = Alpha::DIVQ; break;
|
||||
};
|
||||
switch (N.getValueType()) {
|
||||
default: Node->dump(); assert (0 && "unhandled type");
|
||||
case MVT::f64:
|
||||
assert(N.getOpcode() == ISD::SDIV && "only div here please");
|
||||
Opc = Alpha::DIVT;
|
||||
break;
|
||||
case MVT::f32:
|
||||
assert(N.getOpcode() == ISD::SDIV && "only div here please");
|
||||
Opc = Alpha::DIVS;
|
||||
break;
|
||||
case MVT::i64:
|
||||
//FIXME: alpha really doesn't support any of these operations,
|
||||
// the ops are expanded into special library calls with
|
||||
// special calling conventions
|
||||
switch(N.getOpcode()) {
|
||||
case ISD::UREM: Opc = Alpha::REMQU; break;
|
||||
case ISD::SREM: Opc = Alpha::REMQ; break;
|
||||
case ISD::UDIV: Opc = Alpha::DIVQU; break;
|
||||
case ISD::SDIV: Opc = Alpha::DIVQ; break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
Tmp1 = SelectExpr(N.getOperand(0));
|
||||
Tmp2 = SelectExpr(N.getOperand(1));
|
||||
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
|
||||
return Result;
|
||||
|
||||
// case ISD::SINT_TO_FP:
|
||||
// MVT::ValueType DestTy = N.getValueType();
|
||||
// Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
|
||||
// Tmp2 = MakeReg(DestTy);
|
||||
// Opc = DestTy == MVT::f64 ? ITOFT : ITOFS;
|
||||
// BuildMI(BB, Opc, 1, Tmp2).addReg(Tmp1);
|
||||
// Opc = DestTy == MVT::f64 ? CVTQT : CVTQS;
|
||||
// BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
|
||||
// // case ISD::UINT_TO_FP:
|
||||
|
||||
// case ISD::FP_TO_SINT:
|
||||
// assert (N.getValueType() == MVT::f64 && "Only can convert for doubles");
|
||||
// Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
|
||||
// Tmp2 = MakeReg(SrcTy);
|
||||
// BuildMI(BB, CVTTQ, 1, Tmp2).addReg(Tmp1);
|
||||
// BuildMI(BB, FTOIT, 1, Result).addReg(Tmp2);
|
||||
// return result;
|
||||
|
||||
// // case ISD::FP_TO_UINT:
|
||||
|
||||
case ISD::SELECT:
|
||||
{
|
||||
Tmp2 = SelectExpr(N.getOperand(1)); //Use if TRUE
|
||||
@@ -790,12 +906,17 @@ void ISel::Select(SDOperand N) {
|
||||
std::cerr << N.getNumOperands() << "\n";
|
||||
for (unsigned i = 0; i < N.getNumOperands(); ++i)
|
||||
std::cerr << N.getOperand(i).getValueType() << "\n";
|
||||
Node->dump();
|
||||
assert(0 && "Unknown return instruction!");
|
||||
case 2:
|
||||
Select(N.getOperand(0));
|
||||
Tmp1 = SelectExpr(N.getOperand(1));
|
||||
switch (N.getOperand(1).getValueType()) {
|
||||
default: assert(0 && "All other types should have been promoted!!");
|
||||
default: Node->dump(); assert(0 && "All other types should have been promoted!!");
|
||||
case MVT::f64:
|
||||
case MVT::f32:
|
||||
BuildMI(BB, Alpha::CPYS, 2, Alpha::F0).addReg(Tmp1).addReg(Tmp1);
|
||||
break;
|
||||
case MVT::i32:
|
||||
case MVT::i64:
|
||||
BuildMI(BB, Alpha::BIS, 2, Alpha::R0).addReg(Tmp1).addReg(Tmp1);
|
||||
@@ -839,14 +960,17 @@ void ISel::Select(SDOperand N) {
|
||||
|
||||
case ISD::TRUNCSTORE: { // truncstore chain, val, ptr :storety
|
||||
MVT::ValueType StoredTy = cast<MVTSDNode>(Node)->getExtraValueType();
|
||||
assert(StoredTy != MVT::i64 && "Unsupported TRUNCSTORE for this target!");
|
||||
if (StoredTy == MVT::i64) {
|
||||
Node->dump();
|
||||
assert(StoredTy != MVT::i64 && "Unsupported TRUNCSTORE for this target!");
|
||||
}
|
||||
|
||||
Select(N.getOperand(0));
|
||||
Tmp1 = SelectExpr(N.getOperand(1));
|
||||
Tmp2 = SelectExpr(N.getOperand(2));
|
||||
|
||||
switch (StoredTy) {
|
||||
default: assert(0 && "Unhandled Type"); break;
|
||||
default: Node->dump(); assert(0 && "Unhandled Type"); break;
|
||||
case MVT::i1: //FIXME: DAG does not promote this load
|
||||
case MVT::i8: Opc = Alpha::STB; break;
|
||||
case MVT::i16: Opc = Alpha::STW; break;
|
||||
|
||||
Reference in New Issue
Block a user