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Change SMRange to be half-open (exclusive end) instead of closed (inclusive)

Browse Source 
This is necessary not only for representing empty ranges, but for handling
multibyte characters in the input. (If the end pointer in a range refers to
a multibyte character, should it point to the beginning or the end of the
character in a char array?) Some of the code in the asm parsers was already
assuming this anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171765 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jordan Rose 2013-01-07 19:00:49 +00:00
parent 7aa1c321f0
commit 3ebe59c892
9 changed files with 185 additions and 174 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
include/llvm/Support/SMLoc.h
View File

@ -19,7 +19,7 @@
namespace llvm {
/// SMLoc - Represents a location in source code.
/// Represents a location in source code.
class SMLoc {
const char *Ptr;
public:
@ -39,9 +39,11 @@ public:
}
};
/// SMRange - Represents a range in source code. Note that unlike standard STL
/// ranges, the locations specified are considered to be *inclusive*. For
/// example, [X,X] *does* include X, it isn't an empty range.
/// Represents a range in source code.
///
/// SMRange is implemented using a half-open range, as is the convention in C++.
/// In the string "abc", the range (1,3] represents the substring "bc", and the
/// range (2,2] represents an empty range between the characters "b" and "c".
class SMRange {
public:
SMLoc Start, End;

2
include/llvm/Support/YAMLParser.h
View File

@ -184,7 +184,7 @@ public:
: Node(NK_Scalar, D, Anchor)
, Value(Val) {
SMLoc Start = SMLoc::getFromPointer(Val.begin());
SMLoc End = SMLoc::getFromPointer(Val.end() - 1);
SMLoc End = SMLoc::getFromPointer(Val.end());
SourceRange = SMRange(Start, End);
}

21
lib/MC/MCParser/AsmParser.cpp
View File

@ -732,7 +732,7 @@ bool AsmParser::ParseParenExpr(const MCExpr *&Res, SMLoc &EndLoc) {
if (ParseExpression(Res)) return true;
if (Lexer.isNot(AsmToken::RParen))
return TokError("expected ')' in parentheses expression");
EndLoc = Lexer.getLoc();
EndLoc = Lexer.getTok().getEndLoc();
Lex();
return false;
}
@ -746,7 +746,7 @@ bool AsmParser::ParseBracketExpr(const MCExpr *&Res, SMLoc &EndLoc) {
if (ParseExpression(Res)) return true;
if (Lexer.isNot(AsmToken::RBrac))
return TokError("expected ']' in brackets expression");
EndLoc = Lexer.getLoc();
EndLoc = Lexer.getTok().getEndLoc();
Lex();
return false;
}
@ -773,12 +773,12 @@ bool AsmParser::ParsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) {
case AsmToken::Dollar:
case AsmToken::String:
case AsmToken::Identifier: {
EndLoc = Lexer.getLoc();
StringRef Identifier;
if (ParseIdentifier(Identifier))
return true;
EndLoc = SMLoc::getFromPointer(Identifier.end());
// This is a symbol reference.
std::pair<StringRef, StringRef> Split = Identifier.split('@');
MCSymbol *Sym = getContext().GetOrCreateSymbol(Split.first);
@ -811,7 +811,7 @@ bool AsmParser::ParsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) {
SMLoc Loc = getTok().getLoc();
int64_t IntVal = getTok().getIntVal();
Res = MCConstantExpr::Create(IntVal, getContext());
EndLoc = Lexer.getLoc();
EndLoc = Lexer.getTok().getEndLoc();
Lex(); // Eat token.
// Look for 'b' or 'f' following an Integer as a directional label
if (Lexer.getKind() == AsmToken::Identifier) {
@ -823,7 +823,7 @@ bool AsmParser::ParsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) {
getContext());
if (IDVal == "b" && Sym->isUndefined())
return Error(Loc, "invalid reference to undefined symbol");
EndLoc = Lexer.getLoc();
EndLoc = Lexer.getTok().getEndLoc();
Lex(); // Eat identifier.
}
}
@ -833,6 +833,7 @@ bool AsmParser::ParsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) {
APFloat RealVal(APFloat::IEEEdouble, getTok().getString());
uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
Res = MCConstantExpr::Create(IntVal, getContext());
EndLoc = Lexer.getTok().getEndLoc();
Lex(); // Eat token.
return false;
}
@ -842,7 +843,7 @@ bool AsmParser::ParsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) {
MCSymbol *Sym = Ctx.CreateTempSymbol();
Out.EmitLabel(Sym);
Res = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None, getContext());
EndLoc = Lexer.getLoc();
EndLoc = Lexer.getTok().getEndLoc();
Lex(); // Eat identifier.
return false;
}
@ -1753,7 +1754,7 @@ bool AsmParser::ParseMacroArgument(MacroArgument &MA,
if (IsOperator(Lexer.getKind())) {
// Check to see whether the token is used as an operator,
// or part of an identifier
const char *NextChar = getTok().getEndLoc().getPointer() + 1;
const char *NextChar = getTok().getEndLoc().getPointer();
if (*NextChar == ' ')
AddTokens = 2;
}
@ -2982,7 +2983,7 @@ bool GenericAsmParser::ParseDirectiveLoc(StringRef, SMLoc DirectiveLoc) {
else if (Name == "epilogue_begin")
Flags |= DWARF2_FLAG_EPILOGUE_BEGIN;
else if (Name == "is_stmt") {
SMLoc Loc = getTok().getLoc();
Loc = getTok().getLoc();
const MCExpr *Value;
if (getParser().ParseExpression(Value))
return true;
@ -3001,7 +3002,7 @@ bool GenericAsmParser::ParseDirectiveLoc(StringRef, SMLoc DirectiveLoc) {
}
}
else if (Name == "isa") {
SMLoc Loc = getTok().getLoc();
Loc = getTok().getLoc();
const MCExpr *Value;
if (getParser().ParseExpression(Value))
return true;

2
lib/MC/MCParser/MCAsmLexer.cpp
View File

@ -28,5 +28,5 @@ SMLoc AsmToken::getLoc() const {
}
SMLoc AsmToken::getEndLoc() const {
return SMLoc::getFromPointer(Str.data() + Str.size() - 1);
return SMLoc::getFromPointer(Str.data() + Str.size());
}

2
lib/Support/SourceMgr.cpp
View File

@ -304,7 +304,7 @@ void SMDiagnostic::print(const char *ProgName, raw_ostream &S,
for (unsigned r = 0, e = Ranges.size(); r != e; ++r) {
std::pair<unsigned, unsigned> R = Ranges[r];
for (unsigned i = R.first,
e = std::min(R.second, (unsigned)LineContents.size())+1; i != e; ++i)
e = std::min(R.second, (unsigned)LineContents.size()); i != e; ++i)
CaretLine[i] = '~';
}

172
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -178,7 +178,8 @@ class ARMAsmParser : public MCTargetAsmParser {
OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index);
OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
SMLoc &EndLoc);
// Asm Match Converter Methods
void cvtT2LdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
@ -2450,8 +2451,8 @@ static unsigned MatchRegisterName(StringRef Name);
bool ARMAsmParser::ParseRegister(unsigned &RegNo,
SMLoc &StartLoc, SMLoc &EndLoc) {
StartLoc = Parser.getTok().getLoc();
EndLoc = Parser.getTok().getEndLoc();
RegNo = tryParseRegister();
EndLoc = Parser.getTok().getLoc();
return (RegNo == (unsigned)-1);
}
@ -2540,6 +2541,8 @@ int ARMAsmParser::tryParseShiftRegister(
if (!PrevOp->isReg())
return Error(PrevOp->getStartLoc(), "shift must be of a register");
int SrcReg = PrevOp->getReg();
SMLoc EndLoc;
int64_t Imm = 0;
int ShiftReg = 0;
if (ShiftTy == ARM_AM::rrx) {
@ -2554,7 +2557,7 @@ int ARMAsmParser::tryParseShiftRegister(
Parser.Lex(); // Eat hash.
SMLoc ImmLoc = Parser.getTok().getLoc();
const MCExpr *ShiftExpr = 0;
if (getParser().ParseExpression(ShiftExpr)) {
if (getParser().ParseExpression(ShiftExpr, EndLoc)) {
Error(ImmLoc, "invalid immediate shift value");
return -1;
}
@ -2579,8 +2582,9 @@ int ARMAsmParser::tryParseShiftRegister(
if (Imm == 0)
ShiftTy = ARM_AM::lsl;
} else if (Parser.getTok().is(AsmToken::Identifier)) {
ShiftReg = tryParseRegister();
SMLoc L = Parser.getTok().getLoc();
EndLoc = Parser.getTok().getEndLoc();
ShiftReg = tryParseRegister();
if (ShiftReg == -1) {
Error (L, "expected immediate or register in shift operand");
return -1;
@ -2595,10 +2599,10 @@ int ARMAsmParser::tryParseShiftRegister(
if (ShiftReg && ShiftTy != ARM_AM::rrx)
Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
ShiftReg, Imm,
S, Parser.getTok().getLoc()));
S, EndLoc));
else
Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
S, Parser.getTok().getLoc()));
S, EndLoc));
return 0;
}
@ -2612,12 +2616,13 @@ int ARMAsmParser::tryParseShiftRegister(
/// parse for a specific register type.
bool ARMAsmParser::
tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
SMLoc S = Parser.getTok().getLoc();
const AsmToken &RegTok = Parser.getTok();
int RegNo = tryParseRegister();
if (RegNo == -1)
return true;
Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
RegTok.getEndLoc()));
const AsmToken &ExclaimTok = Parser.getTok();
if (ExclaimTok.is(AsmToken::Exclaim)) {
@ -2641,10 +2646,10 @@ tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
if (!MCE)
return TokError("immediate value expected for vector index");
SMLoc E = Parser.getTok().getLoc();
if (Parser.getTok().isNot(AsmToken::RBrac))
return Error(E, "']' expected");
return Error(Parser.getTok().getLoc(), "']' expected");
SMLoc E = Parser.getTok().getEndLoc();
Parser.Lex(); // Eat right bracket token.
Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
@ -2794,7 +2799,7 @@ parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
// Check for and consume the closing '}'
if (Parser.getTok().isNot(AsmToken::RCurly))
return MatchOperand_ParseFail;
SMLoc E = Parser.getTok().getLoc();
SMLoc E = Parser.getTok().getEndLoc();
Parser.Lex(); // Eat the '}'
Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
@ -2891,10 +2896,10 @@ parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Parser.getTok().is(AsmToken::Minus)) {
if (Parser.getTok().is(AsmToken::Minus)) {
Parser.Lex(); // Eat the minus.
SMLoc EndLoc = Parser.getTok().getLoc();
SMLoc AfterMinusLoc = Parser.getTok().getLoc();
int EndReg = tryParseRegister();
if (EndReg == -1)
return Error(EndLoc, "register expected");
return Error(AfterMinusLoc, "register expected");
// Allow Q regs and just interpret them as the two D sub-registers.
if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
EndReg = getDRegFromQReg(EndReg) + 1;
@ -2904,10 +2909,10 @@ parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
continue;
// The register must be in the same register class as the first.
if (!RC->contains(EndReg))
return Error(EndLoc, "invalid register in register list");
return Error(AfterMinusLoc, "invalid register in register list");
// Ranges must go from low to high.
if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
return Error(EndLoc, "bad range in register list");
return Error(AfterMinusLoc, "bad range in register list");
// Add all the registers in the range to the register list.
while (Reg != EndReg) {
@ -2955,9 +2960,9 @@ parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Registers.push_back(std::pair<unsigned, SMLoc>(++Reg, RegLoc));
}
SMLoc E = Parser.getTok().getLoc();
if (Parser.getTok().isNot(AsmToken::RCurly))
return Error(E, "'}' expected");
return Error(Parser.getTok().getLoc(), "'}' expected");
SMLoc E = Parser.getTok().getEndLoc();
Parser.Lex(); // Eat '}' token.
// Push the register list operand.
@ -2974,13 +2979,14 @@ parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
// Helper function to parse the lane index for vector lists.
ARMAsmParser::OperandMatchResultTy ARMAsmParser::
parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index) {
parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
Index = 0; // Always return a defined index value.
if (Parser.getTok().is(AsmToken::LBrac)) {
Parser.Lex(); // Eat the '['.
if (Parser.getTok().is(AsmToken::RBrac)) {
// "Dn[]" is the 'all lanes' syntax.
LaneKind = AllLanes;
EndLoc = Parser.getTok().getEndLoc();
Parser.Lex(); // Eat the ']'.
return MatchOperand_Success;
}
@ -3005,6 +3011,7 @@ parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index) {
Error(Parser.getTok().getLoc(), "']' expected");
return MatchOperand_ParseFail;
}
EndLoc = Parser.getTok().getEndLoc();
Parser.Lex(); // Eat the ']'.
int64_t Val = CE->getValue();
@ -3031,21 +3038,19 @@ parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
// (without encosing curly braces) as a single or double entry list,
// respectively.
if (Parser.getTok().is(AsmToken::Identifier)) {
SMLoc E = Parser.getTok().getEndLoc();
int Reg = tryParseRegister();
if (Reg == -1)
return MatchOperand_NoMatch;
SMLoc E = Parser.getTok().getLoc();
if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex);
OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
if (Res != MatchOperand_Success)
return Res;
switch (LaneKind) {
case NoLanes:
E = Parser.getTok().getLoc();
Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
break;
case AllLanes:
E = Parser.getTok().getLoc();
Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
S, E));
break;
@ -3059,18 +3064,16 @@ parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
}
if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
Reg = getDRegFromQReg(Reg);
OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex);
OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
if (Res != MatchOperand_Success)
return Res;
switch (LaneKind) {
case NoLanes:
E = Parser.getTok().getLoc();
Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
&ARMMCRegisterClasses[ARM::DPairRegClassID]);
Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
break;
case AllLanes:
E = Parser.getTok().getLoc();
Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
&ARMMCRegisterClasses[ARM::DPairRegClassID]);
Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
@ -3111,7 +3114,9 @@ parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
++Reg;
++Count;
}
if (parseVectorLane(LaneKind, LaneIndex) != MatchOperand_Success)
SMLoc E;
if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
return MatchOperand_ParseFail;
while (Parser.getTok().is(AsmToken::Comma) ||
@ -3125,10 +3130,10 @@ parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
return MatchOperand_ParseFail;
}
Parser.Lex(); // Eat the minus.
SMLoc EndLoc = Parser.getTok().getLoc();
SMLoc AfterMinusLoc = Parser.getTok().getLoc();
int EndReg = tryParseRegister();
if (EndReg == -1) {
Error(EndLoc, "register expected");
Error(AfterMinusLoc, "register expected");
return MatchOperand_ParseFail;
}
// Allow Q regs and just interpret them as the two D sub-registers.
@ -3140,24 +3145,24 @@ parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
continue;
// The register must be in the same register class as the first.
if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
Error(EndLoc, "invalid register in register list");
Error(AfterMinusLoc, "invalid register in register list");
return MatchOperand_ParseFail;
}
// Ranges must go from low to high.
if (Reg > EndReg) {
Error(EndLoc, "bad range in register list");
Error(AfterMinusLoc, "bad range in register list");
return MatchOperand_ParseFail;
}
// Parse the lane specifier if present.
VectorLaneTy NextLaneKind;
unsigned NextLaneIndex;
if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
MatchOperand_Success)
return MatchOperand_ParseFail;
if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
Error(EndLoc, "mismatched lane index in register list");
Error(AfterMinusLoc, "mismatched lane index in register list");
return MatchOperand_ParseFail;
}
EndLoc = Parser.getTok().getLoc();
// Add all the registers in the range to the register list.
Count += EndReg - Reg;
@ -3196,11 +3201,12 @@ parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
// Parse the lane specifier if present.
VectorLaneTy NextLaneKind;
unsigned NextLaneIndex;
SMLoc EndLoc = Parser.getTok().getLoc();
if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
SMLoc LaneLoc = Parser.getTok().getLoc();
if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
MatchOperand_Success)
return MatchOperand_ParseFail;
if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
Error(EndLoc, "mismatched lane index in register list");
Error(LaneLoc, "mismatched lane index in register list");
return MatchOperand_ParseFail;
}
continue;
@ -3221,7 +3227,7 @@ parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
VectorLaneTy NextLaneKind;
unsigned NextLaneIndex;
SMLoc EndLoc = Parser.getTok().getLoc();
if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
return MatchOperand_ParseFail;
if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
Error(EndLoc, "mismatched lane index in register list");
@ -3229,11 +3235,11 @@ parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
}
}
SMLoc E = Parser.getTok().getLoc();
if (Parser.getTok().isNot(AsmToken::RCurly)) {
Error(E, "'}' expected");
Error(Parser.getTok().getLoc(), "'}' expected");
return MatchOperand_ParseFail;
}
E = Parser.getTok().getEndLoc();
Parser.Lex(); // Eat '}' token.
switch (LaneKind) {
@ -3525,7 +3531,8 @@ parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
const MCExpr *ShiftAmount;
SMLoc Loc = Parser.getTok().getLoc();
if (getParser().ParseExpression(ShiftAmount)) {
SMLoc EndLoc;
if (getParser().ParseExpression(ShiftAmount, EndLoc)) {
Error(Loc, "illegal expression");
return MatchOperand_ParseFail;
}
@ -3540,7 +3547,7 @@ parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
return MatchOperand_ParseFail;
}
Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
return MatchOperand_Success;
}
@ -3550,7 +3557,7 @@ parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
const AsmToken &Tok = Parser.getTok();
SMLoc S = Tok.getLoc();
if (Tok.isNot(AsmToken::Identifier)) {
Error(Tok.getLoc(), "'be' or 'le' operand expected");
Error(S, "'be' or 'le' operand expected");
return MatchOperand_ParseFail;
}
int Val = StringSwitch<int>(Tok.getString())
@ -3560,12 +3567,12 @@ parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Parser.Lex(); // Eat the token.
if (Val == -1) {
Error(Tok.getLoc(), "'be' or 'le' operand expected");
Error(S, "'be' or 'le' operand expected");
return MatchOperand_ParseFail;
}
Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
getContext()),
S, Parser.getTok().getLoc()));
S, Tok.getEndLoc()));
return MatchOperand_Success;
}
@ -3601,16 +3608,17 @@ parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
return MatchOperand_ParseFail;
}
Parser.Lex(); // Eat hash token.
SMLoc ExLoc = Parser.getTok().getLoc();
const MCExpr *ShiftAmount;
SMLoc E = Parser.getTok().getLoc();
if (getParser().ParseExpression(ShiftAmount)) {
Error(E, "malformed shift expression");
SMLoc EndLoc;
if (getParser().ParseExpression(ShiftAmount, EndLoc)) {
Error(ExLoc, "malformed shift expression");
return MatchOperand_ParseFail;
}
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
if (!CE) {
Error(E, "shift amount must be an immediate");
Error(ExLoc, "shift amount must be an immediate");
return MatchOperand_ParseFail;
}
@ -3618,25 +3626,24 @@ parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
if (isASR) {
// Shift amount must be in [1,32]
if (Val < 1 || Val > 32) {
Error(E, "'asr' shift amount must be in range [1,32]");
Error(ExLoc, "'asr' shift amount must be in range [1,32]");
return MatchOperand_ParseFail;
}
// asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
if (isThumb() && Val == 32) {
Error(E, "'asr #32' shift amount not allowed in Thumb mode");
Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
return MatchOperand_ParseFail;
}
if (Val == 32) Val = 0;
} else {
// Shift amount must be in [1,32]
if (Val < 0 || Val > 31) {
Error(E, "'lsr' shift amount must be in range [0,31]");
Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
return MatchOperand_ParseFail;
}
}
E = Parser.getTok().getLoc();
Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
return MatchOperand_Success;
}
@ -3662,16 +3669,17 @@ parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
return MatchOperand_ParseFail;
}
Parser.Lex(); // Eat hash token.
SMLoc ExLoc = Parser.getTok().getLoc();
const MCExpr *ShiftAmount;
SMLoc E = Parser.getTok().getLoc();
if (getParser().ParseExpression(ShiftAmount)) {
Error(E, "malformed rotate expression");
SMLoc EndLoc;
if (getParser().ParseExpression(ShiftAmount, EndLoc)) {
Error(ExLoc, "malformed rotate expression");
return MatchOperand_ParseFail;
}
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
if (!CE) {
Error(E, "rotate amount must be an immediate");
Error(ExLoc, "rotate amount must be an immediate");
return MatchOperand_ParseFail;
}
@ -3680,12 +3688,11 @@ parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
// normally, zero is represented in asm by omitting the rotate operand
// entirely.
if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
Error(E, "'ror' rotate amount must be 8, 16, or 24");
Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
return MatchOperand_ParseFail;
}
E = Parser.getTok().getLoc();
Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
return MatchOperand_Success;
}
@ -3735,7 +3742,8 @@ parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Parser.Lex(); // Eat hash token.
const MCExpr *WidthExpr;
if (getParser().ParseExpression(WidthExpr)) {
SMLoc EndLoc;
if (getParser().ParseExpression(WidthExpr, EndLoc)) {
Error(E, "malformed immediate expression");
return MatchOperand_ParseFail;
}
@ -3751,9 +3759,8 @@ parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Error(E, "'width' operand must be in the range [1,32-lsb]");
return MatchOperand_ParseFail;
}
E = Parser.getTok().getLoc();
Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
return MatchOperand_Success;
}
@ -3772,7 +3779,6 @@ parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
SMLoc S = Tok.getLoc();
bool haveEaten = false;
bool isAdd = true;
int Reg = -1;
if (Tok.is(AsmToken::Plus)) {
Parser.Lex(); // Eat the '+' token.
haveEaten = true;
@ -3781,15 +3787,15 @@ parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
isAdd = false;
haveEaten = true;
}
if (Parser.getTok().is(AsmToken::Identifier))
Reg = tryParseRegister();
SMLoc E = Parser.getTok().getEndLoc();
int Reg = tryParseRegister();
if (Reg == -1) {
if (!haveEaten)
return MatchOperand_NoMatch;
Error(Parser.getTok().getLoc(), "register expected");
return MatchOperand_ParseFail;
}
SMLoc E = Parser.getTok().getLoc();
ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
unsigned ShiftImm = 0;
@ -3797,6 +3803,9 @@ parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Parser.Lex(); // Eat the ','.
if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
return MatchOperand_ParseFail;
// FIXME: Only approximates end...may include intervening whitespace.
E = Parser.getTok().getLoc();
}
Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
@ -3829,14 +3838,14 @@ parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
// differently.
bool isNegative = Parser.getTok().is(AsmToken::Minus);
const MCExpr *Offset;
if (getParser().ParseExpression(Offset))
SMLoc E;
if (getParser().ParseExpression(Offset, E))
return MatchOperand_ParseFail;
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
if (!CE) {
Error(S, "constant expression expected");
return MatchOperand_ParseFail;
}
SMLoc E = Tok.getLoc();
// Negative zero is encoded as the flag value INT32_MIN.
int32_t Val = CE->getValue();
if (isNegative && Val == 0)
@ -3851,7 +3860,6 @@ parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
bool haveEaten = false;
bool isAdd = true;
int Reg = -1;
if (Tok.is(AsmToken::Plus)) {
Parser.Lex(); // Eat the '+' token.
haveEaten = true;
@ -3860,18 +3868,18 @@ parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
isAdd = false;
haveEaten = true;
}
if (Parser.getTok().is(AsmToken::Identifier))
Reg = tryParseRegister();
Tok = Parser.getTok();
int Reg = tryParseRegister();
if (Reg == -1) {
if (!haveEaten)
return MatchOperand_NoMatch;
Error(Parser.getTok().getLoc(), "register expected");
Error(Tok.getLoc(), "register expected");
return MatchOperand_ParseFail;
}
SMLoc E = Parser.getTok().getLoc();
Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
0, S, E));
0, S, Tok.getEndLoc()));
return MatchOperand_Success;
}
@ -4224,7 +4232,7 @@ parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
return Error(Tok.getLoc(), "malformed memory operand");
if (Tok.is(AsmToken::RBrac)) {
E = Tok.getLoc();
E = Tok.getEndLoc();
Parser.Lex(); // Eat right bracket token.
Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
@ -4272,9 +4280,9 @@ parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
}
// Now we should have the closing ']'
E = Parser.getTok().getLoc();
if (Parser.getTok().isNot(AsmToken::RBrac))
return Error(E, "']' expected");
return Error(Parser.getTok().getLoc(), "']' expected");
E = Parser.getTok().getEndLoc();
Parser.Lex(); // Eat right bracket token.
// Don't worry about range checking the value here. That's handled by
@ -4321,9 +4329,9 @@ parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
CE = MCConstantExpr::Create(INT32_MIN, getContext());
// Now we should have the closing ']'
E = Parser.getTok().getLoc();
if (Parser.getTok().isNot(AsmToken::RBrac))
return Error(E, "']' expected");
return Error(Parser.getTok().getLoc(), "']' expected");
E = Parser.getTok().getEndLoc();
Parser.Lex(); // Eat right bracket token.
// Don't worry about range checking the value here. That's handled by
@ -4367,9 +4375,9 @@ parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
}
// Now we should have the closing ']'
E = Parser.getTok().getLoc();
if (Parser.getTok().isNot(AsmToken::RBrac))
return Error(E, "']' expected");
return Error(Parser.getTok().getLoc(), "']' expected");
E = Parser.getTok().getEndLoc();
Parser.Lex(); // Eat right bracket token.
Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,

44
lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp
View File

@ -35,7 +35,8 @@ class MBlazeAsmParser : public MCTargetAsmParser {
bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
MBlazeOperand *ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
MBlazeOperand *ParseRegister(unsigned &RegNo);
MBlazeOperand *ParseRegister();
MBlazeOperand *ParseRegister(SMLoc &StartLoc, SMLoc &EndLoc);
MBlazeOperand *ParseImmediate();
MBlazeOperand *ParseFsl();
MBlazeOperand* ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
@ -383,23 +384,31 @@ ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
bool MBlazeAsmParser::ParseRegister(unsigned &RegNo,
SMLoc &StartLoc, SMLoc &EndLoc) {
return (ParseRegister(RegNo) == 0);
MBlazeOperand *Reg = ParseRegister(StartLoc, EndLoc);
if (!Reg)
return true;
RegNo = Reg->getReg();
return false;
}
MBlazeOperand *MBlazeAsmParser::ParseRegister(unsigned &RegNo) {
SMLoc S = Parser.getTok().getLoc();
SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
MBlazeOperand *MBlazeAsmParser::ParseRegister() {
SMLoc S, E;
return ParseRegister(S, E);
}
switch (getLexer().getKind()) {
default: return 0;
case AsmToken::Identifier:
RegNo = MatchRegisterName(getLexer().getTok().getIdentifier());
if (RegNo == 0)
return 0;
MBlazeOperand *MBlazeAsmParser::ParseRegister(SMLoc &StartLoc, SMLoc &EndLoc) {
StartLoc = Parser.getTok().getLoc();
EndLoc = Parser.getTok().getEndLoc();
getLexer().Lex();
return MBlazeOperand::CreateReg(RegNo, S, E);
}
if (getLexer().getKind() != AsmToken::Identifier)
return 0;
unsigned RegNo = MatchRegisterName(getLexer().getTok().getIdentifier());
if (RegNo == 0)
return 0;
getLexer().Lex();
return MBlazeOperand::CreateReg(RegNo, StartLoc, EndLoc);
}
static unsigned MatchFslRegister(StringRef String) {
@ -415,7 +424,7 @@ static unsigned MatchFslRegister(StringRef String) {
MBlazeOperand *MBlazeAsmParser::ParseFsl() {
SMLoc S = Parser.getTok().getLoc();
SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
SMLoc E = Parser.getTok().getEndLoc();
switch (getLexer().getKind()) {
default: return 0;
@ -432,7 +441,7 @@ MBlazeOperand *MBlazeAsmParser::ParseFsl() {
MBlazeOperand *MBlazeAsmParser::ParseImmediate() {
SMLoc S = Parser.getTok().getLoc();
SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
SMLoc E = Parser.getTok().getEndLoc();
const MCExpr *EVal;
switch (getLexer().getKind()) {
@ -454,8 +463,7 @@ ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
MBlazeOperand *Op;
// Attempt to parse the next token as a register name
unsigned RegNo;
Op = ParseRegister(RegNo);
Op = ParseRegister();
// Attempt to parse the next token as an FSL immediate
if (!Op)

50
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
View File

@ -107,7 +107,7 @@ class MipsAsmParser : public MCTargetAsmParser {
bool reportParseError(StringRef ErrorMsg);
bool parseMemOffset(const MCExpr *&Res);
bool parseRelocOperand(const MCExpr *&Res);
bool parseRelocOperand(const MCExpr *&Res, SMLoc &E);
bool parseDirectiveSet();
@ -692,6 +692,7 @@ bool MipsAsmParser::
StringRef Mnemonic){
SMLoc S = Parser.getTok().getLoc();
SMLoc E = Parser.getTok().getEndLoc();
int RegNo = -1;
// FIXME: we should make a more generic method for CCR
@ -706,8 +707,7 @@ bool MipsAsmParser::
if (RegNo == -1)
return true;
Operands.push_back(MipsOperand::CreateReg(RegNo, S,
Parser.getTok().getLoc()));
Operands.push_back(MipsOperand::CreateReg(RegNo, S, E));
Parser.Lex(); // Eat register token.
return false;
}
@ -760,7 +760,7 @@ bool MipsAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*>&Operands,
if (Parser.ParseIdentifier(Identifier))
return true;
SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
SMLoc E = SMLoc::getFromPointer(Identifier.end());
MCSymbol *Sym = getContext().GetOrCreateSymbol("$" + Identifier);
@ -780,9 +780,9 @@ bool MipsAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*>&Operands,
// quoted label names
const MCExpr *IdVal;
SMLoc S = Parser.getTok().getLoc();
if (getParser().ParseExpression(IdVal))
SMLoc E;
if (getParser().ParseExpression(IdVal, E))
return true;
SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
return false;
}
@ -790,11 +790,10 @@ bool MipsAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*>&Operands,
// it is a symbol reference or constant expression
const MCExpr *IdVal;
SMLoc S = Parser.getTok().getLoc(); // start location of the operand
if (parseRelocOperand(IdVal))
SMLoc E;
if (parseRelocOperand(IdVal, E))
return true;
SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
return false;
} // case AsmToken::Percent
@ -802,7 +801,7 @@ bool MipsAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*>&Operands,
return true;
}
bool MipsAsmParser::parseRelocOperand(const MCExpr *&Res) {
bool MipsAsmParser::parseRelocOperand(const MCExpr *&Res, SMLoc &EndLoc) {
Parser.Lex(); // eat % token
const AsmToken &Tok = Parser.getTok(); // get next token, operation
@ -814,7 +813,6 @@ bool MipsAsmParser::parseRelocOperand(const MCExpr *&Res) {
Parser.Lex(); // eat identifier
// now make expression from the rest of the operand
const MCExpr *IdVal;
SMLoc EndLoc;
if (getLexer().getKind() == AsmToken::LParen) {
while (1) {
@ -835,8 +833,10 @@ bool MipsAsmParser::parseRelocOperand(const MCExpr *&Res) {
if (getParser().ParseParenExpression(IdVal,EndLoc))
return true;
while (getLexer().getKind() == AsmToken::RParen)
while (getLexer().getKind() == AsmToken::RParen) {
EndLoc = Parser.getTok().getEndLoc();
Parser.Lex(); // eat ')' token
}
} else
return true; // parenthesis must follow reloc operand
@ -868,24 +868,23 @@ bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) {
StartLoc = Parser.getTok().getLoc();
EndLoc = Parser.getTok().getEndLoc();
RegNo = tryParseRegister("");
EndLoc = Parser.getTok().getLoc();
return (RegNo == (unsigned)-1);
}
bool MipsAsmParser::parseMemOffset(const MCExpr *&Res) {
SMLoc S;
switch(getLexer().getKind()) {
default:
return true;
case AsmToken::Integer:
case AsmToken::Minus:
case AsmToken::Plus:
return (getParser().ParseExpression(Res));
case AsmToken::Percent:
return parseRelocOperand(Res);
return getParser().ParseExpression(Res);
case AsmToken::Percent: {
SMLoc E;
return parseRelocOperand(Res, E);
}
case AsmToken::LParen:
return false; // it's probably assuming 0
}
@ -896,9 +895,8 @@ MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMemOperand(
SmallVectorImpl<MCParsedAsmOperand*>&Operands) {
const MCExpr *IdVal = 0;
SMLoc S;
// first operand is the offset
S = Parser.getTok().getLoc();
SMLoc S = Parser.getTok().getLoc();
SMLoc E = Parser.getTok().getEndLoc();
if (parseMemOffset(IdVal))
return MatchOperand_ParseFail;
@ -907,7 +905,6 @@ MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMemOperand(
if (Tok.isNot(AsmToken::LParen)) {
MipsOperand *Mnemonic = static_cast<MipsOperand*>(Operands[0]);
if (Mnemonic->getToken() == "la") {
SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer()-1);
Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
return MatchOperand_Success;
}
@ -936,8 +933,7 @@ MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMemOperand(
return MatchOperand_ParseFail;
}
SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
E = Parser.getTok().getEndLoc();
Parser.Lex(); // Eat ')' token.
if (IdVal == 0)
@ -1087,8 +1083,8 @@ ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
if (Cc == -1) {
return Error(NameLoc, "Invalid conditional code");
}
SMLoc E = SMLoc::getFromPointer(
Parser.getTok().getLoc().getPointer() -1 );
// FIXME: May include trailing whitespace...
SMLoc E = Parser.getTok().getLoc();
Operands.push_back(MipsOperand::CreateImm(
MCConstantExpr::Create(Cc, getContext()), NameLoc, E));
} else {

56
lib/Target/X86/AsmParser/X86AsmParser.cpp
View File

@ -463,7 +463,7 @@ struct X86Operand : public MCParsedAsmOperand {
}
static X86Operand *CreateToken(StringRef Str, SMLoc Loc) {
SMLoc EndLoc = SMLoc::getFromPointer(Loc.getPointer() + Str.size() - 1);
SMLoc EndLoc = SMLoc::getFromPointer(Loc.getPointer() + Str.size());
X86Operand *Res = new X86Operand(Token, Loc, EndLoc);
Res->Tok.Data = Str.data();
Res->Tok.Length = Str.size();
@ -558,10 +558,12 @@ bool X86AsmParser::ParseRegister(unsigned &RegNo,
Parser.Lex(); // Eat percent token.
const AsmToken &Tok = Parser.getTok();
EndLoc = Tok.getEndLoc();
if (Tok.isNot(AsmToken::Identifier)) {
if (isParsingIntelSyntax()) return true;
return Error(StartLoc, "invalid register name",
SMRange(StartLoc, Tok.getEndLoc()));
SMRange(StartLoc, EndLoc));
}
RegNo = MatchRegisterName(Tok.getString());
@ -582,13 +584,12 @@ bool X86AsmParser::ParseRegister(unsigned &RegNo,
X86II::isX86_64ExtendedReg(RegNo))
return Error(StartLoc, "register %"
+ Tok.getString() + " is only available in 64-bit mode",
SMRange(StartLoc, Tok.getEndLoc()));
SMRange(StartLoc, EndLoc));
}
// Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
if (RegNo == 0 && (Tok.getString() == "st" || Tok.getString() == "ST")) {
RegNo = X86::ST0;
EndLoc = Tok.getLoc();
Parser.Lex(); // Eat 'st'
// Check to see if we have '(4)' after %st.
@ -615,11 +616,13 @@ bool X86AsmParser::ParseRegister(unsigned &RegNo,
if (getParser().Lex().isNot(AsmToken::RParen))
return Error(Parser.getTok().getLoc(), "expected ')'");
EndLoc = Tok.getLoc();
EndLoc = Parser.getTok().getEndLoc();
Parser.Lex(); // Eat ')'
return false;
}
EndLoc = Parser.getTok().getEndLoc();
// If this is "db[0-7]", match it as an alias
// for dr[0-7].
if (RegNo == 0 && Tok.getString().size() == 3 &&
@ -636,7 +639,7 @@ bool X86AsmParser::ParseRegister(unsigned &RegNo,
}
if (RegNo != 0) {
EndLoc = Tok.getLoc();
EndLoc = Parser.getTok().getEndLoc();
Parser.Lex(); // Eat it.
return false;
}
@ -645,10 +648,9 @@ bool X86AsmParser::ParseRegister(unsigned &RegNo,
if (RegNo == 0) {
if (isParsingIntelSyntax()) return true;
return Error(StartLoc, "invalid register name",
SMRange(StartLoc, Tok.getEndLoc()));
SMRange(StartLoc, EndLoc));
}
EndLoc = Tok.getEndLoc();
Parser.Lex(); // Eat identifier token.
return false;
}
@ -677,7 +679,7 @@ X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned SegReg,
unsigned Size) {
unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
const AsmToken &Tok = Parser.getTok();
SMLoc Start = Tok.getLoc(), End;
SMLoc Start = Tok.getLoc(), End = Tok.getEndLoc();
const MCExpr *Disp = MCConstantExpr::Create(0, getContext());
// Parse [ BaseReg + Scale*IndexReg + Disp ] or [ symbol ]
@ -693,9 +695,9 @@ X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned SegReg,
// Handle '[' 'symbol' ']'
if (getParser().ParseExpression(Disp, End)) return 0;
if (getLexer().isNot(AsmToken::RBrac))
return ErrorOperand(Start, "Expected ']' token!");
return ErrorOperand(Parser.getTok().getLoc(), "Expected ']' token!");
End = Parser.getTok().getEndLoc();
Parser.Lex();
End = Tok.getLoc();
return X86Operand::CreateMem(Disp, Start, End, Size);
}
} else if (getLexer().is(AsmToken::Integer)) {
@ -704,8 +706,8 @@ X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned SegReg,
SMLoc Loc = Tok.getLoc();
if (getLexer().is(AsmToken::RBrac)) {
// Handle '[' number ']'
End = Parser.getTok().getEndLoc();
Parser.Lex();
End = Tok.getLoc();
const MCExpr *Disp = MCConstantExpr::Create(Val, getContext());
if (SegReg)
return X86Operand::CreateMem(SegReg, Disp, 0, 0, Scale,
@ -726,8 +728,8 @@ X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned SegReg,
bool ExpectRBrac = true;
if (getLexer().is(AsmToken::RBrac)) {
ExpectRBrac = false;
End = Parser.getTok().getEndLoc();
Parser.Lex();
End = Tok.getLoc();
}
if (getLexer().is(AsmToken::Plus) || getLexer().is(AsmToken::Minus) ||
@ -753,18 +755,18 @@ X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned SegReg,
return ErrorOperand(PlusLoc, "unexpected token after +");
} else if (getLexer().is(AsmToken::Identifier)) {
// This could be an index register or a displacement expression.
End = Tok.getLoc();
if (!IndexReg)
ParseRegister(IndexReg, Start, End);
else if (getParser().ParseExpression(Disp, End)) return 0;
else if (getParser().ParseExpression(Disp, End))
return 0;
}
}
// Parse ][ as a plus.
if (getLexer().is(AsmToken::RBrac)) {
ExpectRBrac = false;
End = Parser.getTok().getEndLoc();
Parser.Lex();
End = Tok.getLoc();
if (getLexer().is(AsmToken::LBrac)) {
ExpectRBrac = true;
Parser.Lex();
@ -772,15 +774,15 @@ X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned SegReg,
return 0;
}
} else if (ExpectRBrac) {
if (getParser().ParseExpression(Disp, End))
return 0;
if (getParser().ParseExpression(Disp, End))
return 0;
}
if (ExpectRBrac) {
if (getLexer().isNot(AsmToken::RBrac))
return ErrorOperand(End, "expected ']' token!");
End = Parser.getTok().getEndLoc();
Parser.Lex();
End = Tok.getLoc();
}
// Parse the dot operator (e.g., [ebx].foo.bar).
@ -790,12 +792,11 @@ X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned SegReg,
if (ParseIntelDotOperator(Disp, &NewDisp, Err))
return ErrorOperand(Tok.getLoc(), Err);
End = Parser.getTok().getEndLoc();
Parser.Lex(); // Eat the field.
Disp = NewDisp;
}
End = Tok.getLoc();
// handle [-42]
if (!BaseReg && !IndexReg)
return X86Operand::CreateMem(Disp, Start, End, Size);
@ -831,8 +832,8 @@ X86Operand *X86AsmParser::ParseIntelMemOperand(unsigned SegReg, SMLoc Start) {
}
const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
if (getParser().ParseExpression(Disp, End)) return 0;
End = Parser.getTok().getLoc();
if (getParser().ParseExpression(Disp, End))
return 0;
bool NeedSizeDir = false;
if (!Size && isParsingInlineAsm()) {
@ -921,8 +922,6 @@ X86Operand *X86AsmParser::ParseIntelOffsetOfOperator(SMLoc Start) {
if (getParser().ParseExpression(Val, End))
return ErrorOperand(Start, "Unable to parse expression!");
End = Parser.getTok().getLoc();
// Don't emit the offset operator.
InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_Skip, OffsetOfLoc, 7));
@ -947,8 +946,6 @@ X86Operand *X86AsmParser::ParseIntelTypeOperator(SMLoc Start) {
if (getParser().ParseExpression(Val, End))
return 0;
End = Parser.getTok().getLoc();
unsigned Size = 0;
if (const MCSymbolRefExpr *SymRef = dyn_cast<MCSymbolRefExpr>(Val)) {
const MCSymbol &Sym = SymRef->getSymbol();
@ -995,7 +992,6 @@ X86Operand *X86AsmParser::ParseIntelOperand() {
getLexer().is(AsmToken::Minus)) {
const MCExpr *Val;
if (!getParser().ParseExpression(Val, End)) {
End = Parser.getTok().getLoc();
return X86Operand::CreateImm(Val, Start, End);
}
}
@ -1006,7 +1002,7 @@ X86Operand *X86AsmParser::ParseIntelOperand() {
// If this is a segment register followed by a ':', then this is the start
// of a memory reference, otherwise this is a normal register reference.
if (getLexer().isNot(AsmToken::Colon))
return X86Operand::CreateReg(RegNo, Start, Parser.getTok().getLoc());
return X86Operand::CreateReg(RegNo, Start, End);
getParser().Lex(); // Eat the colon.
return ParseIntelMemOperand(RegNo, Start);
@ -1183,7 +1179,7 @@ X86Operand *X86AsmParser::ParseMemOperand(unsigned SegReg, SMLoc MemStart) {
Error(Parser.getTok().getLoc(), "unexpected token in memory operand");
return 0;
}
SMLoc MemEnd = Parser.getTok().getLoc();
SMLoc MemEnd = Parser.getTok().getEndLoc();
Parser.Lex(); // Eat the ')'.
// If we have both a base register and an index register make sure they are