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The previous code could potentially cause a cycle. Allow ordering w.r.t. a 0 order.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92810 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2010-01-06 00:23:35 +00:00
parent cfeea4b92a
commit 3f09487404
1 changed files with 2 additions and 2 deletions
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4
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
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@ -1129,8 +1129,8 @@ bool bu_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
// Prefer an ordering where the lower the non-zero order number, the higher
// the preference.
if (LOrder && ROrder && LOrder != ROrder)
return LOrder < ROrder;
if ((LOrder || ROrder) && LOrder != ROrder)
return LOrder != 0 && (LOrder < ROrder || ROrder == 0);
unsigned LPriority = SPQ->getNodePriority(left);
unsigned RPriority = SPQ->getNodePriority(right);