mirror of
https://github.com/c64scene-ar/llvm-6502.git
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AVX-512: Added EXPAND instructions and intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224241 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky
parent
0bf492d3c1
commit
3f2027522c
@ -3584,6 +3584,108 @@ let TargetPrefix = "x86" in {
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GCCBuiltin<"__builtin_ia32_compressstoredi128_mask">,
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Intrinsic<[], [llvm_ptr_ty, llvm_v2i64_ty,
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llvm_i8_ty], [IntrReadWriteArgMem]>;
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// expand
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def int_x86_avx512_mask_expand_ps_512 :
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GCCBuiltin<"__builtin_ia32_expandsf512_mask">,
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Intrinsic<[llvm_v16f32_ty], [llvm_v16f32_ty, llvm_v16f32_ty,
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llvm_i16_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_expand_pd_512 :
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GCCBuiltin<"__builtin_ia32_expanddf512_mask">,
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Intrinsic<[llvm_v8f64_ty], [llvm_v8f64_ty, llvm_v8f64_ty,
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llvm_i8_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_expand_ps_256 :
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GCCBuiltin<"__builtin_ia32_expandsf256_mask">,
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Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty, llvm_v8f32_ty,
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llvm_i8_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_expand_pd_256 :
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GCCBuiltin<"__builtin_ia32_expanddf256_mask">,
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Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty, llvm_v4f64_ty,
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llvm_i8_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_expand_ps_128 :
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GCCBuiltin<"__builtin_ia32_expandsf128_mask">,
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Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty,
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llvm_i8_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_expand_pd_128 :
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GCCBuiltin<"__builtin_ia32_expanddf128_mask">,
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Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty,
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llvm_i8_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_expand_load_ps_512 :
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GCCBuiltin<"__builtin_ia32_expandloadsf512_mask">,
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Intrinsic<[llvm_v16f32_ty], [llvm_ptr_ty, llvm_v16f32_ty,
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llvm_i16_ty], [IntrReadArgMem]>;
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def int_x86_avx512_mask_expand_load_pd_512 :
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GCCBuiltin<"__builtin_ia32_expandloaddf512_mask">,
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Intrinsic<[llvm_v8f64_ty], [llvm_ptr_ty, llvm_v8f64_ty,
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llvm_i8_ty], [IntrReadArgMem]>;
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def int_x86_avx512_mask_expand_load_ps_256 :
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GCCBuiltin<"__builtin_ia32_expandloadsf256_mask">,
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Intrinsic<[llvm_v8f32_ty], [llvm_ptr_ty, llvm_v8f32_ty,
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llvm_i8_ty], [IntrReadArgMem]>;
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def int_x86_avx512_mask_expand_load_pd_256 :
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GCCBuiltin<"__builtin_ia32_expandloaddf256_mask">,
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Intrinsic<[llvm_v4f64_ty], [llvm_ptr_ty, llvm_v4f64_ty,
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llvm_i8_ty], [IntrReadArgMem]>;
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def int_x86_avx512_mask_expand_load_ps_128 :
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GCCBuiltin<"__builtin_ia32_expandloadsf128_mask">,
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Intrinsic<[llvm_v4f32_ty], [llvm_ptr_ty, llvm_v4f32_ty,
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llvm_i8_ty], [IntrReadArgMem]>;
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def int_x86_avx512_mask_expand_load_pd_128 :
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GCCBuiltin<"__builtin_ia32_expandloaddf128_mask">,
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Intrinsic<[llvm_v2f64_ty], [llvm_ptr_ty, llvm_v2f64_ty,
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llvm_i8_ty], [IntrReadArgMem]>;
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def int_x86_avx512_mask_expand_d_512 :
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GCCBuiltin<"__builtin_ia32_expandsi512_mask">,
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Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty, llvm_v16i32_ty,
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llvm_i16_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_expand_q_512 :
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GCCBuiltin<"__builtin_ia32_expanddi512_mask">,
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Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty, llvm_v8i64_ty,
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llvm_i8_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_expand_d_256 :
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GCCBuiltin<"__builtin_ia32_expandsi256_mask">,
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Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty, llvm_v8i32_ty,
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llvm_i8_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_expand_q_256 :
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GCCBuiltin<"__builtin_ia32_expanddi256_mask">,
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Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty, llvm_v4i64_ty,
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llvm_i8_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_expand_d_128 :
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GCCBuiltin<"__builtin_ia32_expandsi128_mask">,
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Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty,
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llvm_i8_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_expand_q_128 :
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GCCBuiltin<"__builtin_ia32_expanddi128_mask">,
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Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty,
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llvm_i8_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_expand_load_d_512 :
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GCCBuiltin<"__builtin_ia32_expandloadsi512_mask">,
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Intrinsic<[llvm_v16i32_ty], [llvm_ptr_ty, llvm_v16i32_ty,
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llvm_i16_ty], [IntrReadArgMem]>;
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def int_x86_avx512_mask_expand_load_q_512 :
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GCCBuiltin<"__builtin_ia32_expandloaddi512_mask">,
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Intrinsic<[llvm_v8i64_ty], [llvm_ptr_ty, llvm_v8i64_ty,
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llvm_i8_ty], [IntrReadArgMem]>;
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def int_x86_avx512_mask_expand_load_d_256 :
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GCCBuiltin<"__builtin_ia32_expandloadsi256_mask">,
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Intrinsic<[llvm_v8i32_ty], [llvm_ptr_ty, llvm_v8i32_ty,
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llvm_i8_ty], [IntrReadArgMem]>;
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def int_x86_avx512_mask_expand_load_q_256 :
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GCCBuiltin<"__builtin_ia32_expandloaddi256_mask">,
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Intrinsic<[llvm_v4i64_ty], [llvm_ptr_ty, llvm_v4i64_ty,
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llvm_i8_ty], [IntrReadArgMem]>;
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def int_x86_avx512_mask_expand_load_d_128 :
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GCCBuiltin<"__builtin_ia32_expandloadsi128_mask">,
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Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_v4i32_ty,
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llvm_i8_ty], [IntrReadArgMem]>;
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def int_x86_avx512_mask_expand_load_q_128 :
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GCCBuiltin<"__builtin_ia32_expandloaddi128_mask">,
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Intrinsic<[llvm_v2i64_ty], [llvm_ptr_ty, llvm_v2i64_ty,
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llvm_i8_ty], [IntrReadArgMem]>;
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}
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// Misc.
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let TargetPrefix = "x86" in {
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@ -16963,7 +16963,7 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget
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Op.getOperand(2), DAG),
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Op.getOperand(4), Op.getOperand(3), Subtarget,
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DAG);
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case COMPRESS_TO_REG: {
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case COMPRESS_EXPAND_IN_REG: {
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SDValue Mask = Op.getOperand(3);
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SDValue DataToCompress = Op.getOperand(1);
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SDValue PassThru = Op.getOperand(2);
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@ -17524,6 +17524,34 @@ static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
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return DAG.getStore(Chain, dl, Compressed, Addr,
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MachinePointerInfo(), false, false, 0);
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}
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case EXPAND_FROM_MEM: {
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SDLoc dl(Op);
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SDValue Mask = Op.getOperand(4);
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SDValue PathThru = Op.getOperand(3);
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SDValue Addr = Op.getOperand(2);
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SDValue Chain = Op.getOperand(0);
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EVT VT = Op.getValueType();
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if (isAllOnes(Mask)) // return just a load
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return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
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false, 0);
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EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
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VT.getVectorNumElements());
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EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
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Mask.getValueType().getSizeInBits());
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SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
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DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
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DAG.getIntPtrConstant(0));
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SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
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false, false, false, 0);
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SmallVector<SDValue, 2> Results;
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Results.push_back(DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToExpand,
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PathThru));
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Results.push_back(Chain);
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return DAG.getMergeValues(Results, dl);
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}
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}
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}
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@ -19710,6 +19738,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
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case X86ISD::XTEST: return "X86ISD::XTEST";
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case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
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case X86ISD::EXPAND: return "X86ISD::EXPAND";
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}
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}
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@ -5323,3 +5323,58 @@ defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info
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defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
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EVEX, VEX_W;
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// expand
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multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
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string OpcodeStr> {
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def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
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(ins _.KRCWM:$mask, _.RC:$src),
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OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
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[(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask, (_.VT _.RC:$src),
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_.ImmAllZerosV)))]>, EVEX_KZ;
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let Constraints = "$src0 = $dst" in
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def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
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(ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
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OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
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[(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
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(_.VT _.RC:$src), _.RC:$src0)))]>, EVEX_K;
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let mayLoad = 1, Constraints = "$src0 = $dst" in
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def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
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(ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src),
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OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
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[(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
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(_.VT (bitconvert
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(_.LdFrag addr:$src))),
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_.RC:$src0)))]>,
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EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
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let mayLoad = 1 in
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def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
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(ins _.KRCWM:$mask, _.MemOp:$src),
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OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
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[(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
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(_.VT (bitconvert (_.LdFrag addr:$src))),
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_.ImmAllZerosV)))]>,
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EVEX_KZ, EVEX_CD8<_.EltSize, CD8VT1>;
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}
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multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
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AVX512VLVectorVTInfo VTInfo> {
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defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
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let Predicates = [HasVLX] in {
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defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
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defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
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}
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}
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defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
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EVEX;
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defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
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EVEX, VEX_W;
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defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
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EVEX;
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defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,
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EVEX, VEX_W;
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@ -286,6 +286,9 @@ def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
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def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 3,
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[SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
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SDTCisVec<3>, SDTCisVec<1>, SDTCisInt<1>]>, []>;
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def X86expand : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 3,
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[SDTCisSameAs<0, 3>,
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SDTCisVec<3>, SDTCisVec<1>, SDTCisInt<1>]>, []>;
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//===----------------------------------------------------------------------===//
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// SSE Complex Patterns
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@ -22,7 +22,7 @@ enum IntrinsicType {
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INTR_TYPE_1OP, INTR_TYPE_2OP, INTR_TYPE_3OP,
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CMP_MASK, CMP_MASK_CC, VSHIFT, VSHIFT_MASK, COMI,
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INTR_TYPE_1OP_MASK_RM, INTR_TYPE_2OP_MASK, INTR_TYPE_SCALAR_MASK_RM,
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COMPRESS_TO_REG, COMPRESS_TO_MEM
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COMPRESS_EXPAND_IN_REG, COMPRESS_TO_MEM, EXPAND_FROM_MEM
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};
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struct IntrinsicData {
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@ -95,7 +95,30 @@ static const IntrinsicData IntrinsicsWithChain[] = {
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COMPRESS_TO_MEM, X86ISD::COMPRESS, 0),
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X86_INTRINSIC_DATA(avx512_mask_compress_store_q_512,
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COMPRESS_TO_MEM, X86ISD::COMPRESS, 0),
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X86_INTRINSIC_DATA(avx512_mask_expand_load_d_128,
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EXPAND_FROM_MEM, X86ISD::EXPAND, 0),
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X86_INTRINSIC_DATA(avx512_mask_expand_load_d_256,
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EXPAND_FROM_MEM, X86ISD::EXPAND, 0),
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X86_INTRINSIC_DATA(avx512_mask_expand_load_d_512,
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EXPAND_FROM_MEM, X86ISD::EXPAND, 0),
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X86_INTRINSIC_DATA(avx512_mask_expand_load_pd_128,
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EXPAND_FROM_MEM, X86ISD::EXPAND, 0),
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X86_INTRINSIC_DATA(avx512_mask_expand_load_pd_256,
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EXPAND_FROM_MEM, X86ISD::EXPAND, 0),
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X86_INTRINSIC_DATA(avx512_mask_expand_load_pd_512,
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EXPAND_FROM_MEM, X86ISD::EXPAND, 0),
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X86_INTRINSIC_DATA(avx512_mask_expand_load_ps_128,
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EXPAND_FROM_MEM, X86ISD::EXPAND, 0),
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X86_INTRINSIC_DATA(avx512_mask_expand_load_ps_256,
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EXPAND_FROM_MEM, X86ISD::EXPAND, 0),
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X86_INTRINSIC_DATA(avx512_mask_expand_load_ps_512,
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EXPAND_FROM_MEM, X86ISD::EXPAND, 0),
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X86_INTRINSIC_DATA(avx512_mask_expand_load_q_128,
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EXPAND_FROM_MEM, X86ISD::EXPAND, 0),
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X86_INTRINSIC_DATA(avx512_mask_expand_load_q_256,
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EXPAND_FROM_MEM, X86ISD::EXPAND, 0),
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X86_INTRINSIC_DATA(avx512_mask_expand_load_q_512,
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EXPAND_FROM_MEM, X86ISD::EXPAND, 0),
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X86_INTRINSIC_DATA(avx512_scatter_dpd_512, SCATTER, X86::VSCATTERDPDZmr, 0),
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X86_INTRINSIC_DATA(avx512_scatter_dpi_512, SCATTER, X86::VPSCATTERDDZmr, 0),
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X86_INTRINSIC_DATA(avx512_scatter_dpq_512, SCATTER, X86::VPSCATTERDQZmr, 0),
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@ -233,30 +256,55 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86_INTRINSIC_DATA(avx512_mask_cmp_w_128, CMP_MASK_CC, X86ISD::CMPM, 0),
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X86_INTRINSIC_DATA(avx512_mask_cmp_w_256, CMP_MASK_CC, X86ISD::CMPM, 0),
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X86_INTRINSIC_DATA(avx512_mask_cmp_w_512, CMP_MASK_CC, X86ISD::CMPM, 0),
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X86_INTRINSIC_DATA(avx512_mask_compress_d_128, COMPRESS_TO_REG,
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X86_INTRINSIC_DATA(avx512_mask_compress_d_128, COMPRESS_EXPAND_IN_REG,
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X86ISD::COMPRESS, 0),
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X86_INTRINSIC_DATA(avx512_mask_compress_d_256, COMPRESS_TO_REG,
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X86_INTRINSIC_DATA(avx512_mask_compress_d_256, COMPRESS_EXPAND_IN_REG,
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X86ISD::COMPRESS, 0),
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X86_INTRINSIC_DATA(avx512_mask_compress_d_512, COMPRESS_TO_REG,
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X86_INTRINSIC_DATA(avx512_mask_compress_d_512, COMPRESS_EXPAND_IN_REG,
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X86ISD::COMPRESS, 0),
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X86_INTRINSIC_DATA(avx512_mask_compress_pd_128, COMPRESS_TO_REG,
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X86_INTRINSIC_DATA(avx512_mask_compress_pd_128, COMPRESS_EXPAND_IN_REG,
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X86ISD::COMPRESS, 0),
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X86_INTRINSIC_DATA(avx512_mask_compress_pd_256, COMPRESS_TO_REG,
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X86_INTRINSIC_DATA(avx512_mask_compress_pd_256, COMPRESS_EXPAND_IN_REG,
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X86ISD::COMPRESS, 0),
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X86_INTRINSIC_DATA(avx512_mask_compress_pd_512, COMPRESS_TO_REG,
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X86_INTRINSIC_DATA(avx512_mask_compress_pd_512, COMPRESS_EXPAND_IN_REG,
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X86ISD::COMPRESS, 0),
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X86_INTRINSIC_DATA(avx512_mask_compress_ps_128, COMPRESS_TO_REG,
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X86_INTRINSIC_DATA(avx512_mask_compress_ps_128, COMPRESS_EXPAND_IN_REG,
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X86ISD::COMPRESS, 0),
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X86_INTRINSIC_DATA(avx512_mask_compress_ps_256, COMPRESS_TO_REG,
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X86_INTRINSIC_DATA(avx512_mask_compress_ps_256, COMPRESS_EXPAND_IN_REG,
|
||||
X86ISD::COMPRESS, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_compress_ps_512, COMPRESS_TO_REG,
|
||||
X86_INTRINSIC_DATA(avx512_mask_compress_ps_512, COMPRESS_EXPAND_IN_REG,
|
||||
X86ISD::COMPRESS, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_compress_q_128, COMPRESS_TO_REG,
|
||||
X86_INTRINSIC_DATA(avx512_mask_compress_q_128, COMPRESS_EXPAND_IN_REG,
|
||||
X86ISD::COMPRESS, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_compress_q_256, COMPRESS_TO_REG,
|
||||
X86_INTRINSIC_DATA(avx512_mask_compress_q_256, COMPRESS_EXPAND_IN_REG,
|
||||
X86ISD::COMPRESS, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_compress_q_512, COMPRESS_TO_REG,
|
||||
X86_INTRINSIC_DATA(avx512_mask_compress_q_512, COMPRESS_EXPAND_IN_REG,
|
||||
X86ISD::COMPRESS, 0),
|
||||
|
||||
X86_INTRINSIC_DATA(avx512_mask_expand_d_128, COMPRESS_EXPAND_IN_REG,
|
||||
X86ISD::EXPAND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_expand_d_256, COMPRESS_EXPAND_IN_REG,
|
||||
X86ISD::EXPAND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_expand_d_512, COMPRESS_EXPAND_IN_REG,
|
||||
X86ISD::EXPAND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_expand_pd_128, COMPRESS_EXPAND_IN_REG,
|
||||
X86ISD::EXPAND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_expand_pd_256, COMPRESS_EXPAND_IN_REG,
|
||||
X86ISD::EXPAND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_expand_pd_512, COMPRESS_EXPAND_IN_REG,
|
||||
X86ISD::EXPAND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_expand_ps_128, COMPRESS_EXPAND_IN_REG,
|
||||
X86ISD::EXPAND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_expand_ps_256, COMPRESS_EXPAND_IN_REG,
|
||||
X86ISD::EXPAND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_expand_ps_512, COMPRESS_EXPAND_IN_REG,
|
||||
X86ISD::EXPAND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_expand_q_128, COMPRESS_EXPAND_IN_REG,
|
||||
X86ISD::EXPAND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_expand_q_256, COMPRESS_EXPAND_IN_REG,
|
||||
X86ISD::EXPAND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_expand_q_512, COMPRESS_EXPAND_IN_REG,
|
||||
X86ISD::EXPAND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_pcmpeq_b_128, CMP_MASK, X86ISD::PCMPEQM, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_pcmpeq_b_256, CMP_MASK, X86ISD::PCMPEQM, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_pcmpeq_b_512, CMP_MASK, X86ISD::PCMPEQM, 0),
|
||||
|
||||
@ -698,3 +698,94 @@ define <4 x i32> @compr10(<4 x i32> %data, i8 %mask) {
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.x86.avx512.mask.compress.d.128(<4 x i32> %data, <4 x i32> %src0, i8 %mask)
|
||||
|
||||
; Expand
|
||||
|
||||
; CHECK-LABEL: expand1
|
||||
; CHECK: vexpandpd (%rdi), %zmm0 {%k1} ## encoding: [0x62,0xf2,0xfd,0x49,0x88,0x07]
|
||||
define <8 x double> @expand1(i8* %addr, <8 x double> %data, i8 %mask) {
|
||||
%res = call <8 x double> @llvm.x86.avx512.mask.expand.load.pd.512(i8* %addr, <8 x double> %data, i8 %mask)
|
||||
ret <8 x double> %res
|
||||
}
|
||||
|
||||
declare <8 x double> @llvm.x86.avx512.mask.expand.load.pd.512(i8* %addr, <8 x double> %data, i8 %mask)
|
||||
|
||||
; CHECK-LABEL: expand2
|
||||
; CHECK: vexpandpd (%rdi), %ymm0 {%k1} ## encoding: [0x62,0xf2,0xfd,0x29,0x88,0x07]
|
||||
define <4 x double> @expand2(i8* %addr, <4 x double> %data, i8 %mask) {
|
||||
%res = call <4 x double> @llvm.x86.avx512.mask.expand.load.pd.256(i8* %addr, <4 x double> %data, i8 %mask)
|
||||
ret <4 x double> %res
|
||||
}
|
||||
|
||||
declare <4 x double> @llvm.x86.avx512.mask.expand.load.pd.256(i8* %addr, <4 x double> %data, i8 %mask)
|
||||
|
||||
; CHECK-LABEL: expand3
|
||||
; CHECK: vexpandps (%rdi), %xmm0 {%k1} ## encoding: [0x62,0xf2,0x7d,0x09,0x88,0x07]
|
||||
define <4 x float> @expand3(i8* %addr, <4 x float> %data, i8 %mask) {
|
||||
%res = call <4 x float> @llvm.x86.avx512.mask.expand.load.ps.128(i8* %addr, <4 x float> %data, i8 %mask)
|
||||
ret <4 x float> %res
|
||||
}
|
||||
|
||||
declare <4 x float> @llvm.x86.avx512.mask.expand.load.ps.128(i8* %addr, <4 x float> %data, i8 %mask)
|
||||
|
||||
; CHECK-LABEL: expand4
|
||||
; CHECK: vexpandpd %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0xc9,0x88,0xc0]
|
||||
define <8 x double> @expand4(i8* %addr, <8 x double> %data, i8 %mask) {
|
||||
%res = call <8 x double> @llvm.x86.avx512.mask.expand.pd.512(<8 x double> %data, <8 x double> zeroinitializer, i8 %mask)
|
||||
ret <8 x double> %res
|
||||
}
|
||||
|
||||
declare <8 x double> @llvm.x86.avx512.mask.expand.pd.512(<8 x double> %data, <8 x double> %src0, i8 %mask)
|
||||
|
||||
; CHECK-LABEL: expand5
|
||||
; CHECK: vexpandpd %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf2,0xfd,0x29,0x88,0xc8]
|
||||
define <4 x double> @expand5(<4 x double> %data, <4 x double> %src0, i8 %mask) {
|
||||
%res = call <4 x double> @llvm.x86.avx512.mask.expand.pd.256( <4 x double> %data, <4 x double> %src0, i8 %mask)
|
||||
ret <4 x double> %res
|
||||
}
|
||||
|
||||
declare <4 x double> @llvm.x86.avx512.mask.expand.pd.256(<4 x double> %data, <4 x double> %src0, i8 %mask)
|
||||
|
||||
; CHECK-LABEL: expand6
|
||||
; CHECK: vexpandps %xmm0
|
||||
define <4 x float> @expand6(<4 x float> %data, i8 %mask) {
|
||||
%res = call <4 x float> @llvm.x86.avx512.mask.expand.ps.128(<4 x float> %data, <4 x float>zeroinitializer, i8 %mask)
|
||||
ret <4 x float> %res
|
||||
}
|
||||
|
||||
declare <4 x float> @llvm.x86.avx512.mask.expand.ps.128(<4 x float> %data, <4 x float> %src0, i8 %mask)
|
||||
|
||||
; CHECK-LABEL: expand7
|
||||
; CHECK-NOT: vexpand
|
||||
; CHECK: vmovapd
|
||||
define <8 x double> @expand7(i8* %addr, <8 x double> %data) {
|
||||
%res = call <8 x double> @llvm.x86.avx512.mask.expand.load.pd.512(i8* %addr, <8 x double> %data, i8 -1)
|
||||
ret <8 x double> %res
|
||||
}
|
||||
|
||||
; CHECK-LABEL: expand8
|
||||
; CHECK-NOT: vexpandps %xmm0
|
||||
define <4 x float> @expand8(<4 x float> %data) {
|
||||
%res = call <4 x float> @llvm.x86.avx512.mask.expand.ps.128(<4 x float> %data, <4 x float>zeroinitializer, i8 -1)
|
||||
ret <4 x float> %res
|
||||
}
|
||||
|
||||
; CHECK-LABEL: expand9
|
||||
; CHECK: vpexpandq (%rdi), %zmm0 {%k1} ## encoding: [0x62,0xf2,0xfd,0x49,0x89,0x07]
|
||||
define <8 x i64> @expand9(i8* %addr, <8 x i64> %data, i8 %mask) {
|
||||
%res = call <8 x i64> @llvm.x86.avx512.mask.expand.load.q.512(i8* %addr, <8 x i64> %data, i8 %mask)
|
||||
ret <8 x i64> %res
|
||||
}
|
||||
|
||||
declare <8 x i64> @llvm.x86.avx512.mask.expand.load.q.512(i8* %addr, <8 x i64> %data, i8 %mask)
|
||||
|
||||
; CHECK-LABEL: expand10
|
||||
; CHECK: vpexpandd %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf2,0x7d,0x89,0x89,0xc0]
|
||||
define <4 x i32> @expand10(<4 x i32> %data, i8 %mask) {
|
||||
%res = call <4 x i32> @llvm.x86.avx512.mask.expand.d.128(<4 x i32> %data, <4 x i32>zeroinitializer, i8 %mask)
|
||||
ret <4 x i32> %res
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.x86.avx512.mask.expand.d.128(<4 x i32> %data, <4 x i32> %src0, i8 %mask)
|
||||
|
||||
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user