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If scheduler choice is the default (-sched=default), use target scheduling
preference to determine which scheduler to use. SchedulingForLatency == Breadth first; SchedulingForRegPressure == bottom up register reduction list scheduler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25599 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -59,8 +59,10 @@ namespace {
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ISHeuristic(
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"sched",
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cl::desc("Choose scheduling style"),
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cl::init(noScheduling),
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cl::init(defaultScheduling),
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cl::values(
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clEnumValN(defaultScheduling, "default",
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"Target preferred scheduling style"),
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clEnumValN(noScheduling, "none",
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"No scheduling: breadth first sequencing"),
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clEnumValN(simpleScheduling, "simple",
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@ -69,7 +71,7 @@ namespace {
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clEnumValN(simpleNoItinScheduling, "simple-noitin",
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"Simple two pass scheduling: Same as simple "
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"except using generic latency"),
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clEnumValN(listSchedulingBURR, "list-BURR",
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clEnumValN(listSchedulingBURR, "list-burr",
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"Bottom up register reduction list scheduling"),
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clEnumValEnd));
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} // namespace
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@ -1772,6 +1774,12 @@ void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
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switch (ISHeuristic) {
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default: assert(0 && "Unrecognized scheduling heuristic");
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case defaultScheduling:
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if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
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SL = createSimpleDAGScheduler(noScheduling, DAG, BB);
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else /* TargetLowering::SchedulingForRegPressure */
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SL = createBURRListDAGScheduler(DAG, BB);
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break;
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case noScheduling:
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case simpleScheduling:
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case simpleNoItinScheduling:
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