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If scheduler choice is the default (-sched=default), use target scheduling

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preference to determine which scheduler to use. SchedulingForLatency ==
Breadth first; SchedulingForRegPressure == bottom up register reduction list
scheduler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25599 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2006-01-25 09:12:57 +00:00
parent d854b62afa
commit 3f23952404
1 changed files with 10 additions and 2 deletions
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12
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
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@ -59,8 +59,10 @@ namespace {
ISHeuristic( ISHeuristic(
"sched", "sched",
cl::desc("Choose scheduling style"), cl::desc("Choose scheduling style"),
cl::init(noScheduling), cl::init(defaultScheduling),
cl::values( cl::values(
clEnumValN(defaultScheduling, "default",
"Target preferred scheduling style"),
clEnumValN(noScheduling, "none", clEnumValN(noScheduling, "none",
"No scheduling: breadth first sequencing"), "No scheduling: breadth first sequencing"),
clEnumValN(simpleScheduling, "simple", clEnumValN(simpleScheduling, "simple",
@ -69,7 +71,7 @@ namespace {
clEnumValN(simpleNoItinScheduling, "simple-noitin", clEnumValN(simpleNoItinScheduling, "simple-noitin",
"Simple two pass scheduling: Same as simple " "Simple two pass scheduling: Same as simple "
"except using generic latency"), "except using generic latency"),
clEnumValN(listSchedulingBURR, "list-BURR", clEnumValN(listSchedulingBURR, "list-burr",
"Bottom up register reduction list scheduling"), "Bottom up register reduction list scheduling"),
clEnumValEnd)); clEnumValEnd));
} // namespace } // namespace
@ -1772,6 +1774,12 @@ void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
switch (ISHeuristic) { switch (ISHeuristic) {
default: assert(0 && "Unrecognized scheduling heuristic"); default: assert(0 && "Unrecognized scheduling heuristic");
case defaultScheduling:
if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
SL = createSimpleDAGScheduler(noScheduling, DAG, BB);
else /* TargetLowering::SchedulingForRegPressure */
SL = createBURRListDAGScheduler(DAG, BB);
break;
case noScheduling: case noScheduling:
case simpleScheduling: case simpleScheduling:
case simpleNoItinScheduling: case simpleNoItinScheduling: