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AArch64/ARM64: add dp tests from AArch64

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206281 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2014-04-15 13:59:40 +00:00
parent 86a70cd2f5
commit 3f2d713f4d
4 changed files with 19 additions and 11 deletions
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5
lib/Target/ARM64/ARM64InstrInfo.td
View File

@ -666,6 +666,11 @@ def REVXr : OneXRegData<0b011, "rev", bswap>;
def REV32Xr : OneXRegData<0b010, "rev32",
UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>;
// The bswap commutes with the rotr so we want a pattern for both possible
// orders.
def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>;
def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>;
//===----------------------------------------------------------------------===//
// Bitfield immediate extraction instruction.
//===----------------------------------------------------------------------===//

1
test/CodeGen/AArch64/dp-3source.ll
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@ -1,4 +1,5 @@
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 | FileCheck %s
define i32 @test_madd32(i32 %val0, i32 %val1, i32 %val2) {
; CHECK-LABEL: test_madd32:

1
test/CodeGen/AArch64/dp1.ll
View File

@ -1,4 +1,5 @@
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-linux-gnu | FileCheck %s
@var32 = global i32 0
@var64 = global i64 0

23
test/CodeGen/AArch64/dp2.ll
View File

@ -1,4 +1,5 @@
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64 | FileCheck %s
@var32_0 = global i32 0
@var32_1 = global i32 0
@ -13,7 +14,7 @@ define void @rorv_i64() {
%val3_tmp = shl i64 %val0_tmp, %val2_tmp
%val4_tmp = lshr i64 %val0_tmp, %val1_tmp
%val5_tmp = or i64 %val3_tmp, %val4_tmp
; CHECK: ror {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
; CHECK: {{ror|rorv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
store volatile i64 %val5_tmp, i64* @var64_0
ret void
}
@ -23,7 +24,7 @@ define void @asrv_i64() {
%val0_tmp = load i64* @var64_0
%val1_tmp = load i64* @var64_1
%val4_tmp = ashr i64 %val0_tmp, %val1_tmp
; CHECK: asr {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
; CHECK: {{asr|asrv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
store volatile i64 %val4_tmp, i64* @var64_1
ret void
}
@ -33,7 +34,7 @@ define void @lsrv_i64() {
%val0_tmp = load i64* @var64_0
%val1_tmp = load i64* @var64_1
%val4_tmp = lshr i64 %val0_tmp, %val1_tmp
; CHECK: lsr {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
; CHECK: {{lsr|lsrv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
store volatile i64 %val4_tmp, i64* @var64_0
ret void
}
@ -43,7 +44,7 @@ define void @lslv_i64() {
%val0_tmp = load i64* @var64_0
%val1_tmp = load i64* @var64_1
%val4_tmp = shl i64 %val0_tmp, %val1_tmp
; CHECK: lsl {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
; CHECK: {{lsl|lslv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
store volatile i64 %val4_tmp, i64* @var64_1
ret void
}
@ -75,7 +76,7 @@ define void @lsrv_i32() {
%val1_tmp = load i32* @var32_1
%val2_tmp = add i32 1, %val1_tmp
%val4_tmp = lshr i32 %val0_tmp, %val2_tmp
; CHECK: lsr {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
; CHECK: {{lsr|lsrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
store volatile i32 %val4_tmp, i32* @var32_0
ret void
}
@ -86,7 +87,7 @@ define void @lslv_i32() {
%val1_tmp = load i32* @var32_1
%val2_tmp = add i32 1, %val1_tmp
%val4_tmp = shl i32 %val0_tmp, %val2_tmp
; CHECK: lsl {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
; CHECK: {{lsl|lslv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
store volatile i32 %val4_tmp, i32* @var32_1
ret void
}
@ -100,7 +101,7 @@ define void @rorv_i32() {
%val3_tmp = shl i32 %val0_tmp, %val2_tmp
%val4_tmp = lshr i32 %val0_tmp, %val1_tmp
%val5_tmp = or i32 %val3_tmp, %val4_tmp
; CHECK: ror {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
; CHECK: {{ror|rorv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
store volatile i32 %val5_tmp, i32* @var32_0
ret void
}
@ -111,7 +112,7 @@ define void @asrv_i32() {
%val1_tmp = load i32* @var32_1
%val2_tmp = add i32 1, %val1_tmp
%val4_tmp = ashr i32 %val0_tmp, %val2_tmp
; CHECK: asr {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
; CHECK: {{asr|asrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
store volatile i32 %val4_tmp, i32* @var32_1
ret void
}
@ -143,7 +144,7 @@ define i32 @test_lsl32() {
%val = load i32* @var32_0
%ret = shl i32 1, %val
; CHECK: lsl {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
; CHECK: {{lsl|lslv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
ret i32 %ret
}
@ -153,7 +154,7 @@ define i32 @test_lsr32() {
%val = load i32* @var32_0
%ret = lshr i32 1, %val
; CHECK: lsr {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
; CHECK: {{lsr|lsrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
ret i32 %ret
}
@ -163,7 +164,7 @@ define i32 @test_asr32(i32 %in) {
%val = load i32* @var32_0
%ret = ashr i32 %in, %val
; CHECK: asr {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
; CHECK: {{asr|asrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
ret i32 %ret
}