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Add SSSE3 as a feature of Core2. Add MMX registers to the list of registers
clobbered by a call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36448 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -64,7 +64,7 @@ def : Proc<"prescott", [FeatureMMX, FeatureSSE1, FeatureSSE2,
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def : Proc<"nocona", [FeatureMMX, FeatureSSE1, FeatureSSE2,
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FeatureSSE3, Feature64Bit]>;
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def : Proc<"core2", [FeatureMMX, FeatureSSE1, FeatureSSE2,
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FeatureSSE3, Feature64Bit]>;
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FeatureSSE3, FeatureSSSE3, Feature64Bit]>;
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def : Proc<"k6", [FeatureMMX]>;
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def : Proc<"k6-2", [FeatureMMX, Feature3DNow]>;
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@ -458,6 +458,7 @@ def JNO : IBr<0x81, (ops brtarget:$dst), "jno $dst",
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let isCall = 1, noResults = 1 in
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// All calls clobber the non-callee saved registers...
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let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
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MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
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XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7] in {
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def CALLpcrel32 : I<0xE8, RawFrm, (ops i32imm:$dst, variable_ops),
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"call ${dst:call}", []>;
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