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Add simple arithmetics and %type directive for PTX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119485 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -64,14 +64,26 @@ static const char PARAM_PREFIX[] = "__param_";
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static const char *getRegisterTypeName(unsigned RegNo){
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#define TEST_REGCLS(cls, clsstr) \
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if (PTX::cls ## RegisterClass->contains(RegNo)) return # clsstr;
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TEST_REGCLS(RRegs32, .s32);
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TEST_REGCLS(Preds, .pred);
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TEST_REGCLS(RRegs32, s32);
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TEST_REGCLS(Preds, pred);
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#undef TEST_REGCLS
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llvm_unreachable("Not in any register class!");
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return NULL;
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}
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static const char *getInstructionTypeName(const MachineInstr *MI)
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{
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for (int i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (MO.getType() == MachineOperand::MO_Register)
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return getRegisterTypeName(MO.getReg());
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}
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llvm_unreachable("No reg operand found in instruction!");
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return NULL;
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}
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bool PTXAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
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SetupMachineFunction(MF);
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EmitFunctionDeclaration();
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@ -89,7 +101,7 @@ void PTXAsmPrinter::EmitFunctionBodyStart() {
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i = MFI->localVarRegBegin(), e = MFI->localVarRegEnd(); i != e; ++ i) {
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unsigned reg = *i;
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std::string def = "\t.reg ";
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std::string def = "\t.reg .";
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def += getRegisterTypeName(reg);
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def += ' ';
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def += getRegisterName(reg);
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@ -99,11 +111,21 @@ void PTXAsmPrinter::EmitFunctionBodyStart() {
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}
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void PTXAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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SmallString<128> str;
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raw_svector_ostream OS(str);
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SmallString<128> sstr;
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raw_svector_ostream OS(sstr);
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printInstruction(MI, OS);
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OS << ';';
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OutStreamer.EmitRawText(OS.str());
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// Replace "%type" if found
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StringRef strref = OS.str();
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size_t pos;
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if ((pos = strref.find("%type")) == StringRef::npos) {
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OutStreamer.EmitRawText(strref);
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return;
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}
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std::string str = strref;
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str.replace(pos, /*strlen("%type")==*/5, getInstructionTypeName(MI));
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OutStreamer.EmitRawText(StringRef(str));
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}
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void PTXAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
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@ -141,7 +163,7 @@ void PTXAsmPrinter::EmitFunctionDeclaration() {
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// Print return register
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reg = MFI->retReg();
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if (!isKernel && reg != PTX::NoRegister) {
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decl += " (.reg "; // FIXME: could it return in .param space?
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decl += " (.reg ."; // FIXME: could it return in .param space?
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decl += getRegisterTypeName(reg);
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decl += " ";
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decl += getRegisterName(reg);
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@ -170,7 +192,7 @@ void PTXAsmPrinter::EmitFunctionDeclaration() {
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assert(reg != PTX::NoRegister && "Not a valid register!");
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if (i != b)
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decl += ", ";
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decl += ".reg ";
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decl += ".reg .";
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decl += getRegisterTypeName(reg);
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decl += " ";
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decl += getRegisterName(reg);
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@ -26,10 +26,30 @@ def PTXexit
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def PTXret
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: SDNode<"PTXISD::RET", SDTNone, [SDNPHasChain]>;
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//===----------------------------------------------------------------------===//
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// Instruction Class Templates
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//===----------------------------------------------------------------------===//
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multiclass INT3<string opcstr, SDNode opnode> {
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def rr : InstPTX<(outs RRegs32:$d),
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(ins RRegs32:$a, RRegs32:$b),
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!strconcat(opcstr, ".%type\t$d, $a, $b"),
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[(set RRegs32:$d, (opnode RRegs32:$a, RRegs32:$b))]>;
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def ri : InstPTX<(outs RRegs32:$d),
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(ins RRegs32:$a, i32imm:$b),
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!strconcat(opcstr, ".%type\t$d, $a, $b"),
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[(set RRegs32:$d, (opnode RRegs32:$a, imm:$b))]>;
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}
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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///===- Integer Arithmetic Instructions -----------------------------------===//
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defm ADD : INT3<"add", add>;
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defm SUB : INT3<"sub", sub>;
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///===- Data Movement and Conversion Instructions -------------------------===//
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let neverHasSideEffects = 1 in {
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@ -37,7 +57,7 @@ let neverHasSideEffects = 1 in {
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def MOVpp
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: InstPTX<(outs Preds:$d), (ins Preds:$a), "mov.pred\t$d, $a", []>;
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def MOVrr
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: InstPTX<(outs RRegs32:$d), (ins RRegs32:$a), "mov.s32\t$d, $a", []>;
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: InstPTX<(outs RRegs32:$d), (ins RRegs32:$a), "mov.%type\t$d, $a", []>;
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}
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let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
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15
test/CodeGen/PTX/add.ll
Normal file
15
test/CodeGen/PTX/add.ll
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@ -0,0 +1,15 @@
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; RUN: llc < %s -march=ptx | FileCheck %s
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define ptx_device i32 @t1(i32 %x, i32 %y) {
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; CHECK: add.s32 r0, r1, r2;
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%z = add i32 %x, %y
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; CHECK: ret;
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ret i32 %z
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}
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define ptx_device i32 @t2(i32 %x) {
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; CHECK: add.s32 r0, r1, 1;
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%z = add i32 %x, 1
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; CHECK: ret;
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ret i32 %z
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}
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@ -2,5 +2,6 @@
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define ptx_kernel void @t1() {
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; CHECK: exit;
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; CHECK-NOT: ret;
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ret void
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}
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@ -2,5 +2,6 @@
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define ptx_device void @t1() {
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; CHECK: ret;
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; CHECK-NOT: exit;
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ret void
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}
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15
test/CodeGen/PTX/sub.ll
Normal file
15
test/CodeGen/PTX/sub.ll
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@ -0,0 +1,15 @@
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; RUN: llc < %s -march=ptx | FileCheck %s
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define ptx_device i32 @t1(i32 %x, i32 %y) {
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;CHECK: sub.s32 r0, r1, r2;
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%z = sub i32 %x, %y
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;CHECK: ret;
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ret i32 %z
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}
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define ptx_device i32 @t2(i32 %x) {
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;CHECK: add.s32 r0, r1, -1;
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%z = sub i32 %x, 1
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;CHECK: ret;
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ret i32 %z
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}
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