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Testing convertToThreeeAddress as X86 llcbeta.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42630 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -22,8 +22,15 @@
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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namespace {
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cl::opt<bool>
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EnableConvert3Addr("enable-x86-conv-3-addr",
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cl::desc("Enable convertToThreeAddress for X86"));
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}
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X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
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: TargetInstrInfo(X86Insts, array_lengthof(X86Insts)),
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TM(tm), RI(tm, *this) {
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@ -144,6 +151,21 @@ bool X86InstrInfo::isReallyTriviallyReMaterializable(MachineInstr *MI) const {
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return true;
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}
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/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
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/// is not marked dead.
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static bool hasLiveCondCodeDef(MachineInstr *MI) {
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if (!EnableConvert3Addr)
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return true;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isRegister() && MO.isDef() &&
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MO.getReg() == X86::EFLAGS && !MO.isDead()) {
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return true;
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}
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}
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return false;
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}
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/// convertToThreeAddress - This method must be implemented by targets that
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/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
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/// may be able to convert a two-address instruction into a true
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@ -169,7 +191,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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bool DisableLEA16 = true;
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switch (MI->getOpcode()) {
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default: return 0;
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default: break; // All others need to check for live condition code defs.
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case X86::SHUFPSrri: {
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assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
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if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
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@ -253,10 +275,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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}
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}
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// FIXME: None of these instructions are promotable to LEAs without
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// additional information. In particular, LEA doesn't set the flags that
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// add and inc do. :(
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if (0)
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if (!hasLiveCondCodeDef(MI))
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switch (MI->getOpcode()) {
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case X86::INC32r:
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case X86::INC64_32r:
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