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Bug fix. X86 was emitting redundant setcc and test instructions before a conditional move.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42774 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3705,33 +3705,30 @@ SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
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if (Cond.getOpcode() == ISD::SETCC)
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if (Cond.getOpcode() == ISD::SETCC)
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Cond = LowerSETCC(Cond, DAG);
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Cond = LowerSETCC(Cond, DAG);
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// If condition flag is set by a X86ISD::CMP, then use it as the condition
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// setting operand in place of the X86ISD::SETCC.
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if (Cond.getOpcode() == X86ISD::SETCC) {
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if (Cond.getOpcode() == X86ISD::SETCC) {
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CC = Cond.getOperand(0);
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CC = Cond.getOperand(0);
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// If condition flag is set by a X86ISD::CMP, then make a copy of it
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// (since flag operand cannot be shared). Use it as the condition setting
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// operand in place of the X86ISD::SETCC.
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// If the X86ISD::SETCC has more than one use, then perhaps it's better
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// to use a test instead of duplicating the X86ISD::CMP (for register
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// pressure reason)?
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SDOperand Cmp = Cond.getOperand(1);
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SDOperand Cmp = Cond.getOperand(1);
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unsigned Opc = Cmp.getOpcode();
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unsigned Opc = Cmp.getOpcode();
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bool IllegalFPCMov =
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MVT::ValueType VT = Op.getValueType();
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! ((X86ScalarSSEf32 && Op.getValueType()==MVT::f32) ||
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bool IllegalFPCMov = false;
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(X86ScalarSSEf64 && Op.getValueType()==MVT::f64)) &&
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if (VT == MVT::f32 && !X86ScalarSSEf32)
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!hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
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IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
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else if (VT == MVT::f64 && !X86ScalarSSEf64)
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IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
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if ((Opc == X86ISD::CMP ||
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if ((Opc == X86ISD::CMP ||
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Opc == X86ISD::COMI ||
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Opc == X86ISD::COMI ||
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Opc == X86ISD::UCOMI) && !IllegalFPCMov) {
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Opc == X86ISD::UCOMI) && !IllegalFPCMov) {
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Cond = DAG.getNode(Opc, MVT::i32, Cmp.getOperand(0), Cmp.getOperand(1));
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Cond = Cmp;
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addTest = false;
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addTest = false;
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}
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}
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}
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}
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if (addTest) {
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if (addTest) {
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CC = DAG.getConstant(X86::COND_NE, MVT::i8);
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CC = DAG.getConstant(X86::COND_NE, MVT::i8);
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Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Cond,
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Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
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DAG.getConstant(0, MVT::i8));
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}
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}
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const MVT::ValueType *VTs = DAG.getNodeValueTypes(Op.getValueType(),
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const MVT::ValueType *VTs = DAG.getNodeValueTypes(Op.getValueType(),
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@ -3756,21 +3753,17 @@ SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
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if (Cond.getOpcode() == ISD::SETCC)
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if (Cond.getOpcode() == ISD::SETCC)
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Cond = LowerSETCC(Cond, DAG);
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Cond = LowerSETCC(Cond, DAG);
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// If condition flag is set by a X86ISD::CMP, then use it as the condition
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// setting operand in place of the X86ISD::SETCC.
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if (Cond.getOpcode() == X86ISD::SETCC) {
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if (Cond.getOpcode() == X86ISD::SETCC) {
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CC = Cond.getOperand(0);
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CC = Cond.getOperand(0);
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// If condition flag is set by a X86ISD::CMP, then make a copy of it
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// (since flag operand cannot be shared). Use it as the condition setting
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// operand in place of the X86ISD::SETCC.
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// If the X86ISD::SETCC has more than one use, then perhaps it's better
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// to use a test instead of duplicating the X86ISD::CMP (for register
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// pressure reason)?
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SDOperand Cmp = Cond.getOperand(1);
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SDOperand Cmp = Cond.getOperand(1);
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unsigned Opc = Cmp.getOpcode();
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unsigned Opc = Cmp.getOpcode();
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if (Opc == X86ISD::CMP ||
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if (Opc == X86ISD::CMP ||
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Opc == X86ISD::COMI ||
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Opc == X86ISD::COMI ||
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Opc == X86ISD::UCOMI) {
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Opc == X86ISD::UCOMI) {
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Cond = DAG.getNode(Opc, MVT::i32, Cmp.getOperand(0), Cmp.getOperand(1));
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Cond = Cmp;
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addTest = false;
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addTest = false;
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}
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}
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}
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}
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