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Even more spelling fixes for "instruction".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191611 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -66,7 +66,7 @@ namespace llvm {
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}
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/// Returns true if this value is defined by a PHI instruction (or was,
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/// PHI instrucions may have been eliminated).
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/// PHI instructions may have been eliminated).
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/// PHI-defs begin at a block boundary, all other defs begin at register or
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/// EC slots.
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bool isPHIDef() const { return def.isBlock(); }
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@ -410,8 +410,8 @@ public:
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/// branch to do so (e.g., a table jump). True is a conservative answer.
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bool canFallThrough();
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/// Returns a pointer to the first instructon in this block that is not a
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/// PHINode instruction. When adding instruction to the beginning of the
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/// Returns a pointer to the first instruction in this block that is not a
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/// PHINode instruction. When adding instructions to the beginning of the
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/// basic block, they should be added before the returned value, not before
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/// the first instruction, which might be PHI.
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/// Returns end() is there's no non-PHI instruction.
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@ -129,7 +129,7 @@ namespace llvm {
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Reg2SUnitsMap Defs;
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Reg2SUnitsMap Uses;
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/// Track the last instructon in this region defining each virtual register.
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/// Track the last instruction in this region defining each virtual register.
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VReg2SUnitMap VRegDefs;
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/// PendingLoads - Remember where unknown loads are after the most recent
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@ -76,7 +76,7 @@ def instregex;
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// See MCSchedule.h for detailed comments.
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class SchedMachineModel {
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int IssueWidth = -1; // Max micro-ops that may be scheduled per cycle.
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int MinLatency = -1; // Determines which instrucions are allowed in a group.
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int MinLatency = -1; // Determines which instructions are allowed in a group.
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// (-1) inorder (0) ooo, (1): inorder +var latencies.
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int MicroOpBufferSize = -1; // Max micro-ops that can be buffered.
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int LoadLatency = -1; // Cycles for loads to access the cache.
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@ -847,7 +847,7 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
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case ARM::MOVsrl_flag:
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case ARM::MOVsra_flag: {
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// These are just fancy MOVs insructions.
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// These are just fancy MOVs instructions.
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AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
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MI.getOperand(0).getReg())
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.addOperand(MI.getOperand(1))
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@ -426,7 +426,7 @@ rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx,
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*this);
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} else {
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// Translate r0 = add sp, -imm to
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// r0 = -imm (this is then translated into a series of instructons)
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// r0 = -imm (this is then translated into a series of instructions)
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// r0 = add r0, sp
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emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl);
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@ -63,7 +63,7 @@ class MemAccessSize<bits<3> value> {
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def NoMemAccess : MemAccessSize<0>;// Not a memory acces instruction.
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def ByteAccess : MemAccessSize<1>;// Byte access instruction (memb).
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def HalfWordAccess : MemAccessSize<2>;// Half word access instruction (memh).
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def WordAccess : MemAccessSize<3>;// Word access instrution (memw).
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def WordAccess : MemAccessSize<3>;// Word access instruction (memw).
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def DoubleWordAccess : MemAccessSize<4>;// Double word access instruction (memd)
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@ -29,7 +29,7 @@
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//
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// Note: The peephole pass makes the instrucstions like
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// %vreg170<def> = SXTW %vreg166 or %vreg16<def> = NOT_p %vreg15<kill>
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// redundant and relies on some form of dead removal instrucions, like
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// redundant and relies on some form of dead removal instructions, like
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// DCE or DIE to actually eliminate them.
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@ -73,7 +73,7 @@ namespace HexagonII {
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NoMemAccess = 0, // Not a memory acces instruction.
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ByteAccess = 1, // Byte access instruction (memb).
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HalfWordAccess = 2, // Half word access instruction (memh).
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WordAccess = 3, // Word access instrution (memw).
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WordAccess = 3, // Word access instruction (memw).
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DoubleWordAccess = 4 // Double word access instruction (memd)
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};
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@ -22,7 +22,7 @@ namespace llvm {
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};
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typedef SmallVector<Inst, 7 > InstSeq;
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/// Analyze - Get an instrucion sequence to load immediate Imm. The last
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/// Analyze - Get an instruction sequence to load immediate Imm. The last
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/// instruction in the sequence must be an ADDiu if LastInstrIsADDiu is
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/// true;
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const InstSeq &Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu);
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@ -32,19 +32,19 @@ namespace llvm {
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/// AddInstr - Add I to all instruction sequences in SeqLs.
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void AddInstr(InstSeqLs &SeqLs, const Inst &I);
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/// GetInstSeqLsADDiu - Get instrucion sequences which end with an ADDiu to
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/// GetInstSeqLsADDiu - Get instruction sequences which end with an ADDiu to
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/// load immediate Imm
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void GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs);
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/// GetInstSeqLsORi - Get instrucion sequences which end with an ORi to
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/// GetInstSeqLsORi - Get instrutcion sequences which end with an ORi to
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/// load immediate Imm
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void GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs);
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/// GetInstSeqLsSLL - Get instrucion sequences which end with a SLL to
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/// GetInstSeqLsSLL - Get instruction sequences which end with a SLL to
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/// load immediate Imm
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void GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs);
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/// GetInstSeqLs - Get instrucion sequences to load immediate Imm.
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/// GetInstSeqLs - Get instruction sequences to load immediate Imm.
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void GetInstSeqLs(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs);
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/// ReplaceADDiuSLLWithLUi - Replace an ADDiu & SLL pair with a LUi.
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@ -115,7 +115,7 @@ def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
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// Wrapper node patterns give the instruction selector a chance to replace
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// target constant nodes that would otherwise remain unchanged with ADDiu
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// nodes. Without these wrapper node patterns, the following conditional move
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// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
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// instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
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// compiled:
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// movn %got(d)($gp), %got(c)($gp), $4
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// This instruction is illegal since movn can take only register operands.
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@ -275,7 +275,7 @@ bool AMDGPUIndirectAddressingPass::runOnMachineFunction(MachineFunction &MF) {
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} else {
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// Indirect register access
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// Note on REQ_SEQUENCE instructons: You can't actually use the register
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// Note on REQ_SEQUENCE instructions: You can't actually use the register
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// it defines unless you have an instruction that takes the defined
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// register class as an operand.
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@ -314,7 +314,7 @@ bool NclPopcountRecognize::preliminaryScreen() {
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if (TTI->getPopcntSupport(32) != TargetTransformInfo::PSK_FastHardware)
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return false;
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// Counting population are usually conducted by few arithmetic instrutions.
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// Counting population are usually conducted by few arithmetic instructions.
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// Such instructions can be easilly "absorbed" by vacant slots in a
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// non-compact loop. Therefore, recognizing popcount idiom only makes sense
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// in a compact loop.
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@ -1357,7 +1357,7 @@ void InnerLoopVectorizer::scalarizeInstruction(Instruction *Instr) {
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Instruction *Cloned = Instr->clone();
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if (!IsVoidRetTy)
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Cloned->setName(Instr->getName() + ".cloned");
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// Replace the operands of the cloned instrucions with extracted scalars.
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// Replace the operands of the cloned instructions with extracted scalars.
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for (unsigned op = 0, e = Instr->getNumOperands(); op != e; ++op) {
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Value *Op = Params[op][Part];
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// Param is a vector. Need to extract the right lane.
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@ -4901,7 +4901,7 @@ void InnerLoopUnroller::scalarizeInstruction(Instruction *Instr) {
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Instruction *Cloned = Instr->clone();
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if (!IsVoidRetTy)
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Cloned->setName(Instr->getName() + ".cloned");
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// Replace the operands of the cloned instrucions with extracted scalars.
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// Replace the operands of the cloned instructions with extracted scalars.
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for (unsigned op = 0, e = Instr->getNumOperands(); op != e; ++op) {
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Value *Op = Params[op][Part];
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Cloned->setOperand(op, Op);
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@ -318,7 +318,7 @@ private:
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/// \returns the pointer to the barrier instruction if we can't sink.
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Value *getSinkBarrier(Instruction *Src, Instruction *Dst);
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/// \returns the index of the last instrucion in the BB from \p VL.
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/// \returns the index of the last instruction in the BB from \p VL.
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int getLastIndex(ArrayRef<Value *> VL);
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/// \returns the Instruction in the bundle \p VL.
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