6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-19 19:29:31 +00:00
Code Issues Projects Releases Wiki Activity

Allow legalizer to expand ISD::MUL using only MULHS in the rare case that is

Browse Source 
possible and the target only supports MULHS.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30022 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2006-09-01 18:17:58 +00:00
parent 3ebe71db6b
commit 3f4fd0fd64
1 changed files with 13 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -4656,7 +4656,10 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
break;
}
case ISD::MUL: {
if (TLI.isOperationLegal(ISD::MULHU, NVT)) {
bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
bool UseLibCall = true;
if (HasMULHS || HasMULHU) {
SDOperand LL, LH, RL, RH;
ExpandOp(Node->getOperand(0), LL, LH);
ExpandOp(Node->getOperand(1), RL, RH);
@ -4665,7 +4668,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
// extended the sign bit of the low half through the upper half, and if so
// emit a MULHS instead of the alternate sequence that is valid for any
// i64 x i64 multiply.
if (TLI.isOperationLegal(ISD::MULHS, NVT) &&
if (HasMULHS &&
// is RH an extension of the sign bit of RL?
RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
RH.getOperand(1).getOpcode() == ISD::Constant &&
@ -4675,17 +4678,21 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
LH.getOperand(1).getOpcode() == ISD::Constant &&
cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
} else {
UseLibCall = false;
} else if (HasMULHU) {
Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
UseLibCall = false;
}
Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
} else {
Lo = ExpandLibCall("__muldi3" , Node, Hi);
if (!UseLibCall)
Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
}
if (UseLibCall)
Lo = ExpandLibCall("__muldi3" , Node, Hi);
break;
}
case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break;