mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-25 00:29:20 +00:00
Remove more opcode special cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72454 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eli Friedman
parent
f1a80489d6
commit
3f727d6c1b
@ -125,7 +125,9 @@ private:
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/// is necessary to spill the vector being inserted into to memory, perform
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/// the insert there, and then read the result back.
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SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
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SDValue Idx, DebugLoc dl);
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SDValue Idx, DebugLoc dl);
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SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
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SDValue Idx, DebugLoc dl);
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/// Useful 16 element vector type that is used to pass operands for widening.
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typedef SmallVector<SDValue, 16> SDValueVector;
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@ -683,6 +685,33 @@ PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
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}
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SDValue SelectionDAGLegalize::
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ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) {
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if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
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// SCALAR_TO_VECTOR requires that the type of the value being inserted
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// match the element type of the vector being created, except for
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// integers in which case the inserted value can be over width.
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MVT EltVT = Vec.getValueType().getVectorElementType();
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if (Val.getValueType() == EltVT ||
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(EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
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SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
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Vec.getValueType(), Val);
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unsigned NumElts = Vec.getValueType().getVectorNumElements();
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// We generate a shuffle of InVec and ScVec, so the shuffle mask
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// should be 0,1,2,3,4,5... with the appropriate element replaced with
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// elt 0 of the RHS.
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SmallVector<int, 8> ShufOps;
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for (unsigned i = 0; i != NumElts; ++i)
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ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
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return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
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&ShufOps[0]);
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}
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}
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return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
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}
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/// LegalizeOp - We know that the specified value has a legal type, and
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/// that its operands are legal. Now ensure that the operation itself
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/// is legal, recursively ensuring that the operands' operations remain
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@ -861,22 +890,6 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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#endif
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assert(0 && "Do not know how to legalize this operator!");
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abort();
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case ISD::GLOBAL_OFFSET_TABLE:
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case ISD::GlobalAddress:
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case ISD::GlobalTLSAddress:
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case ISD::ExternalSymbol:
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case ISD::ConstantPool:
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case ISD::JumpTable: // Nothing to do.
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switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
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default: assert(0 && "This action is not supported yet!");
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case TargetLowering::Custom:
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Tmp1 = TLI.LowerOperation(Op, DAG);
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if (Tmp1.getNode()) Result = Tmp1;
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// FALLTHROUGH if the target doesn't want to lower this op after all.
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case TargetLowering::Legal:
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break;
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}
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break;
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case ISD::EXCEPTIONADDR: {
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Tmp1 = LegalizeOp(Node->getOperand(0));
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MVT VT = Node->getValueType(0);
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@ -944,33 +957,6 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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AddLegalizedOperand(Op.getValue(0), Tmp1);
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AddLegalizedOperand(Op.getValue(1), Tmp2);
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return Op.getResNo() ? Tmp2 : Tmp1;
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case ISD::INTRINSIC_W_CHAIN:
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case ISD::INTRINSIC_WO_CHAIN:
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case ISD::INTRINSIC_VOID: {
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SmallVector<SDValue, 8> Ops;
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for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
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Ops.push_back(LegalizeOp(Node->getOperand(i)));
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Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
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// Allow the target to custom lower its intrinsics if it wants to.
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if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
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TargetLowering::Custom) {
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Tmp3 = TLI.LowerOperation(Result, DAG);
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if (Tmp3.getNode()) Result = Tmp3;
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}
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if (Result.getNode()->getNumValues() == 1) break;
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// Must have return value and chain result.
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assert(Result.getNode()->getNumValues() == 2 &&
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"Cannot return more than two values!");
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// Since loads produce two values, make sure to remember that we
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// legalized both of them.
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AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
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AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
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return Result.getValue(Op.getResNo());
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}
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case ISD::DBG_STOPPOINT:
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assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
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@ -1115,62 +1101,6 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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break;
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}
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break;
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case ISD::INSERT_VECTOR_ELT:
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Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
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Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
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// The type of the value to insert may not be legal, even though the vector
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// type is legal. Legalize/Promote accordingly. We do not handle Expand
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// here.
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Tmp2 = LegalizeOp(Node->getOperand(1));
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Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
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switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
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Node->getValueType(0))) {
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default: assert(0 && "This action is not supported yet!");
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case TargetLowering::Legal:
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break;
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case TargetLowering::Custom:
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Tmp4 = TLI.LowerOperation(Result, DAG);
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if (Tmp4.getNode()) {
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Result = Tmp4;
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break;
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}
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// FALLTHROUGH
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case TargetLowering::Promote:
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// Fall thru for vector case
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case TargetLowering::Expand: {
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// If the insert index is a constant, codegen this as a scalar_to_vector,
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// then a shuffle that inserts it into the right position in the vector.
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if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
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// SCALAR_TO_VECTOR requires that the type of the value being inserted
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// match the element type of the vector being created, except for
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// integers in which case the inserted value can be over width.
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MVT EltVT = Op.getValueType().getVectorElementType();
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if (Tmp2.getValueType() == EltVT ||
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(EltVT.isInteger() && Tmp2.getValueType().bitsGE(EltVT))) {
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SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
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Tmp1.getValueType(), Tmp2);
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unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
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// We generate a shuffle of InVec and ScVec, so the shuffle mask
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// should be 0,1,2,3,4,5... with the appropriate element replaced with
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// elt 0 of the RHS.
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SmallVector<int, 8> ShufOps;
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for (unsigned i = 0; i != NumElts; ++i)
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ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
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Result = DAG.getVectorShuffle(Tmp1.getValueType(), dl, Tmp1, ScVec,
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&ShufOps[0]);
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Result = LegalizeOp(Result);
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break;
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}
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}
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Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3, dl);
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break;
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}
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}
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break;
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case ISD::VECTOR_SHUFFLE: {
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Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
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Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
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@ -1976,65 +1906,6 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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}
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break;
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}
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case ISD::STACKSAVE:
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Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
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Result = DAG.UpdateNodeOperands(Result, Tmp1);
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Tmp1 = Result.getValue(0);
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Tmp2 = Result.getValue(1);
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switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
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default: assert(0 && "This action is not supported yet!");
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case TargetLowering::Legal: break;
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case TargetLowering::Custom:
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Tmp3 = TLI.LowerOperation(Result, DAG);
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if (Tmp3.getNode()) {
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Tmp1 = LegalizeOp(Tmp3);
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Tmp2 = LegalizeOp(Tmp3.getValue(1));
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}
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break;
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case TargetLowering::Expand:
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// Expand to CopyFromReg if the target set
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// StackPointerRegisterToSaveRestore.
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if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
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Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), dl, SP,
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Node->getValueType(0));
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Tmp2 = Tmp1.getValue(1);
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} else {
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Tmp1 = DAG.getUNDEF(Node->getValueType(0));
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Tmp2 = Node->getOperand(0);
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}
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break;
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}
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// Since stacksave produce two values, make sure to remember that we
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// legalized both of them.
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AddLegalizedOperand(SDValue(Node, 0), Tmp1);
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AddLegalizedOperand(SDValue(Node, 1), Tmp2);
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return Op.getResNo() ? Tmp2 : Tmp1;
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case ISD::STACKRESTORE:
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Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
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Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
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Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
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switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
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default: assert(0 && "This action is not supported yet!");
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case TargetLowering::Legal: break;
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case TargetLowering::Custom:
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Tmp1 = TLI.LowerOperation(Result, DAG);
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if (Tmp1.getNode()) Result = Tmp1;
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break;
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case TargetLowering::Expand:
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// Expand to CopyToReg if the target set
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// StackPointerRegisterToSaveRestore.
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if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
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Result = DAG.getCopyToReg(Tmp1, dl, SP, Tmp2);
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} else {
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Result = Tmp1;
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}
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break;
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}
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break;
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case ISD::SELECT:
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Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
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Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
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@ -3654,6 +3525,11 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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case ISD::SCALAR_TO_VECTOR:
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Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
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break;
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case ISD::INSERT_VECTOR_ELT:
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Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
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Node->getOperand(1),
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Node->getOperand(2), dl));
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break;
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case ISD::EXTRACT_ELEMENT: {
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MVT OpTy = Node->getOperand(0).getValueType();
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if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
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@ -3670,6 +3546,41 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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Results.push_back(Tmp1);
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break;
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}
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case ISD::STACKSAVE:
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// Expand to CopyFromReg if the target set
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// StackPointerRegisterToSaveRestore.
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if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
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Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
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Node->getValueType(0)));
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Results.push_back(Results[0].getValue(1));
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} else {
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Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
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Results.push_back(Node->getOperand(0));
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}
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break;
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case ISD::STACKRESTORE:
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// Expand to CopyToReg if the target set
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// StackPointerRegisterToSaveRestore.
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if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
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Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
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Node->getOperand(1)));
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} else {
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Results.push_back(Node->getOperand(0));
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}
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break;
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case ISD::GLOBAL_OFFSET_TABLE:
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case ISD::GlobalAddress:
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case ISD::GlobalTLSAddress:
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case ISD::ExternalSymbol:
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case ISD::ConstantPool:
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case ISD::JumpTable:
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case ISD::INTRINSIC_W_CHAIN:
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case ISD::INTRINSIC_WO_CHAIN:
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case ISD::INTRINSIC_VOID:
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// FIXME: Custom lowering for these operations shouldn't return null!
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for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
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Results.push_back(SDValue(Node, i));
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break;
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}
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}
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void SelectionDAGLegalize::PromoteNode(SDNode *Node,
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