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MFLR doesn't take an operand, the LR register is implicit

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22882 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-08-18 23:24:50 +00:00
parent 329cdc3801
commit 3f852b45fc
3 changed files with 3 additions and 3 deletions
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2
lib/Target/PowerPC/PPC32ISelSimple.cpp
View File

@ -619,7 +619,7 @@ unsigned PPC32ISel::getGlobalBaseReg() {
MachineBasicBlock::iterator MBBI = FirstMBB.begin();
GlobalBaseReg = makeAnotherReg(Type::IntTy);
BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg).addReg(PPC::LR);
BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg);
GlobalBaseInitialized = true;
}
return GlobalBaseReg;

2
lib/Target/PowerPC/PPCISelPattern.cpp
View File

@ -437,7 +437,7 @@ unsigned ISel::getGlobalBaseReg() {
MachineBasicBlock::iterator MBBI = FirstMBB.begin();
GlobalBaseReg = MakeIntReg();
BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg).addReg(PPC::LR);
BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg);
GlobalBaseInitialized = true;
}
return GlobalBaseReg;

2
lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -83,7 +83,7 @@ PPC32RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
};
unsigned OC = Opcode[getIdx(getClass(SrcReg))];
if (SrcReg == PPC::LR) {
BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11).addReg(PPC::LR);
BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R11),FrameIdx);
} else if (PPC32::CRRCRegisterClass == getClass(SrcReg)) {
BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11);