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Fix a problem that occurs when PHI nodes have multiple entries for the same predecessor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5055 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -283,43 +283,60 @@ void RegAllocSimple::EliminatePHINodes(MachineBasicBlock &MBB) {
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const TargetRegisterClass* regClass = PhysRegClasses[physReg];
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const TargetRegisterClass* regClass = PhysRegClasses[physReg];
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assert(regClass && "Target register class not found!");
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assert(regClass && "Target register class not found!");
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unsigned dataSize = regClass->getDataSize();
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unsigned dataSize = regClass->getDataSize();
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for (int i = MI->getNumOperands() - 1; i >= 2; i-=2) {
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for (int i = MI->getNumOperands() - 1; i >= 2; i-=2) {
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MachineOperand &opVal = MI->getOperand(i-1);
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MachineOperand &opVal = MI->getOperand(i-1);
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// Get the MachineBasicBlock equivalent of the BasicBlock that is the
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// Get the MachineBasicBlock equivalent of the BasicBlock that is the
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// source path the phi
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// source path the phi
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MachineBasicBlock &opBlock = *MI->getOperand(i).getMachineBasicBlock();
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MachineBasicBlock &opBlock = *MI->getOperand(i).getMachineBasicBlock();
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MachineBasicBlock::iterator opI = opBlock.end();
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MachineInstr *opMI = *--opI;
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// must backtrack over ALL the branches in the previous block, until no
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// Check to make sure we haven't already emitted the copy for this block.
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// more
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// This can happen because PHI nodes may have multiple entries for the
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while (MII.isBranch(opMI->getOpcode()) && opI != opBlock.begin())
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// same basic block. It doesn't matter which entry we use though, because
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opMI = *--opI;
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// all incoming values are guaranteed to be the same for a particular bb.
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//
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// Note that this is N^2 in the number of phi node entries, but since the
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// # of entries is tiny, this is not a problem.
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//
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bool HaveNotEmitted = true;
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for (int op = MI->getNumOperands() - 1; op != i; op -= 2)
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if (&opBlock == MI->getOperand(op).getMachineBasicBlock()) {
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HaveNotEmitted = false;
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break;
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}
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// move back to the first branch instruction so new instructions
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if (HaveNotEmitted) {
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// are inserted right in front of it and not in front of a non-branch
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MachineBasicBlock::iterator opI = opBlock.end();
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if (!MII.isBranch(opMI->getOpcode()))
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MachineInstr *opMI = *--opI;
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++opI;
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// must backtrack over ALL the branches in the previous block
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// Retrieve the constant value from this op, move it to target
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while (MII.isBranch(opMI->getOpcode()) && opI != opBlock.begin())
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// register of the phi
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opMI = *--opI;
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if (opVal.isImmediate()) {
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opI = RegInfo->moveImm2Reg(opBlock, opI, physReg,
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// move back to the first branch instruction so new instructions
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(unsigned) opVal.getImmedValue(),
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// are inserted right in front of it and not in front of a non-branch
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dataSize);
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if (!MII.isBranch(opMI->getOpcode()))
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saveVirtRegToStack(opBlock, opI, virtualReg, physReg);
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++opI;
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} else {
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// Allocate a physical register and add a move in the BB
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// Retrieve the constant value from this op, move it to target
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unsigned opVirtualReg = (unsigned) opVal.getAllocatedRegNum();
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// register of the phi
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unsigned opPhysReg;
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if (opVal.isImmediate()) {
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opI = moveUseToReg(opBlock, opI, opVirtualReg, physReg);
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opI = RegInfo->moveImm2Reg(opBlock, opI, physReg,
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(unsigned) opVal.getImmedValue(),
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// Save that register value to the stack of the TARGET REG
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dataSize);
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saveVirtRegToStack(opBlock, opI, virtualReg, physReg);
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saveVirtRegToStack(opBlock, opI, virtualReg, physReg);
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} else {
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// Allocate a physical register and add a move in the BB
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unsigned opVirtualReg = (unsigned) opVal.getAllocatedRegNum();
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unsigned opPhysReg;
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opI = moveUseToReg(opBlock, opI, opVirtualReg, physReg);
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// Save that register value to the stack of the TARGET REG
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saveVirtRegToStack(opBlock, opI, virtualReg, physReg);
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}
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}
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}
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// make regs available to other instructions
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// make regs available to other instructions
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clearAllRegs();
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clearAllRegs();
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}
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}
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