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https://github.com/c64scene-ar/llvm-6502.git
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[Hexagon] Adding indexed store of immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225006 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu
parent
65971bbfd7
commit
3fa758981d
@ -694,9 +694,9 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
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case Hexagon::L2_loadrub_pi:
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return isInt<4>(MI->getOperand(3).getImm());
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case Hexagon::STrib_imm_V4:
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case Hexagon::STrih_imm_V4:
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case Hexagon::STriw_imm_V4:
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case Hexagon::S4_storeirb_io:
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case Hexagon::S4_storeirh_io:
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case Hexagon::S4_storeiri_io:
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return (isUInt<6>(MI->getOperand(1).getImm()) &&
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isInt<6>(MI->getOperand(2).getImm()));
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@ -1420,8 +1420,8 @@ isConditionalStore (const MachineInstr* MI) const {
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switch (MI->getOpcode())
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{
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default: return false;
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case Hexagon::STrib_imm_cPt_V4 :
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case Hexagon::STrib_imm_cNotPt_V4 :
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case Hexagon::S4_storeirbt_io:
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case Hexagon::S4_storeirbf_io:
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case Hexagon::S4_pstorerbt_rr:
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case Hexagon::S4_pstorerbf_rr:
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case Hexagon::S2_pstorerbt_io:
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@ -1436,16 +1436,16 @@ isConditionalStore (const MachineInstr* MI) const {
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case Hexagon::S2_pstorerdf_pi:
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case Hexagon::S2_pstorerht_io:
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case Hexagon::S2_pstorerhf_io:
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case Hexagon::STrih_imm_cPt_V4 :
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case Hexagon::STrih_imm_cNotPt_V4 :
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case Hexagon::S4_storeirht_io:
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case Hexagon::S4_storeirhf_io:
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case Hexagon::S4_pstorerht_rr:
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case Hexagon::S4_pstorerhf_rr:
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case Hexagon::S2_pstorerht_pi:
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case Hexagon::S2_pstorerhf_pi:
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case Hexagon::S2_pstorerit_io:
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case Hexagon::S2_pstorerif_io:
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case Hexagon::STriw_imm_cPt_V4 :
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case Hexagon::STriw_imm_cNotPt_V4 :
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case Hexagon::S4_storeirit_io:
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case Hexagon::S4_storeirif_io:
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case Hexagon::S4_pstorerit_rr:
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case Hexagon::S4_pstorerif_rr:
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case Hexagon::S2_pstorerit_pi:
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@ -906,75 +906,124 @@ defm : T_ST_LOff_Pats<STrih_shl_V4, IntRegs, i32, truncstorei16>;
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// if ([!]Pv[.new]) memd(#u6)=Rtt
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// TODO: needs to be implemented.
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//===----------------------------------------------------------------------===//
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// Template class
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//===----------------------------------------------------------------------===//
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let isPredicable = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 8,
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opExtendable = 2 in
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class T_StoreImm <string mnemonic, Operand OffsetOp, bits<2> MajOp >
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: STInst <(outs ), (ins IntRegs:$Rs, OffsetOp:$offset, s8Ext:$S8),
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mnemonic#"($Rs+#$offset)=#$S8",
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[], "", V4LDST_tc_st_SLOT01>,
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ImmRegRel, PredNewRel {
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bits<5> Rs;
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bits<8> S8;
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bits<8> offset;
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bits<6> offsetBits;
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string OffsetOpStr = !cast<string>(OffsetOp);
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let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2},
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!if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1},
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/* u6_0Imm */ offset{5-0}));
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let IClass = 0b0011;
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let Inst{27-25} = 0b110;
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let Inst{22-21} = MajOp;
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let Inst{20-16} = Rs;
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let Inst{12-7} = offsetBits;
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let Inst{13} = S8{7};
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let Inst{6-0} = S8{6-0};
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}
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let isPredicated = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 6,
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opExtendable = 3 in
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class T_StoreImm_pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
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bit isPredNot, bit isPredNew >
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: STInst <(outs ),
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(ins PredRegs:$Pv, IntRegs:$Rs, OffsetOp:$offset, s6Ext:$S6),
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!if(isPredNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
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") ")#mnemonic#"($Rs+#$offset)=#$S6",
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[], "", V4LDST_tc_st_SLOT01>,
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ImmRegRel, PredNewRel {
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bits<2> Pv;
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bits<5> Rs;
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bits<6> S6;
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bits<8> offset;
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bits<6> offsetBits;
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string OffsetOpStr = !cast<string>(OffsetOp);
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let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2},
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!if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1},
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/* u6_0Imm */ offset{5-0}));
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let isPredicatedNew = isPredNew;
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let isPredicatedFalse = isPredNot;
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let IClass = 0b0011;
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let Inst{27-25} = 0b100;
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let Inst{24} = isPredNew;
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let Inst{23} = isPredNot;
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let Inst{22-21} = MajOp;
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let Inst{20-16} = Rs;
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let Inst{13} = S6{5};
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let Inst{12-7} = offsetBits;
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let Inst{6-5} = Pv;
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let Inst{4-0} = S6{4-0};
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}
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//===----------------------------------------------------------------------===//
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// multiclass for store instructions with base + immediate offset
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// addressing mode and immediate stored value.
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// mem[bhw](Rx++#s4:3)=#s8
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// if ([!]Pv[.new]) mem[bhw](Rx++#s4:3)=#s6
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//===----------------------------------------------------------------------===//
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multiclass ST_Imm_Pbase<string mnemonic, Operand OffsetOp, bit isNot,
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bit isPredNew> {
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let isPredicatedNew = isPredNew in
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def NAME : STInst2<(outs),
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(ins PredRegs:$src1, IntRegs:$src2, OffsetOp:$src3, s6Ext:$src4),
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!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
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") ")#mnemonic#"($src2+#$src3) = #$src4",
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[]>,
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Requires<[HasV4T]>;
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multiclass ST_Imm_Pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
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bit PredNot> {
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def _io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 0>;
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// Predicate new
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def new_io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 1>;
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}
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multiclass ST_Imm_Pred<string mnemonic, Operand OffsetOp, bit PredNot> {
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let isPredicatedFalse = PredNot in {
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defm _c#NAME : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 0>;
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// Predicate new
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defm _cdn#NAME : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 1>;
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}
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}
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let isExtendable = 1, isExtentSigned = 1, hasSideEffects = 0 in
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multiclass ST_Imm<string mnemonic, string CextOp, Operand OffsetOp> {
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multiclass ST_Imm <string mnemonic, string CextOp, Operand OffsetOp,
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bits<2> MajOp> {
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let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in {
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let opExtendable = 2, opExtentBits = 8, isPredicable = 1 in
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def NAME#_V4 : STInst2<(outs),
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(ins IntRegs:$src1, OffsetOp:$src2, s8Ext:$src3),
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mnemonic#"($src1+#$src2) = #$src3",
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[]>,
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Requires<[HasV4T]>;
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def _io : T_StoreImm <mnemonic, OffsetOp, MajOp>;
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let opExtendable = 3, opExtentBits = 6, isPredicated = 1 in {
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defm Pt_V4 : ST_Imm_Pred<mnemonic, OffsetOp, 0>;
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defm NotPt_V4 : ST_Imm_Pred<mnemonic, OffsetOp, 1 >;
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}
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defm t : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 0>;
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defm f : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 1>;
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}
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}
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let addrMode = BaseImmOffset, InputType = "imm",
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validSubTargets = HasV4SubT in {
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let hasSideEffects = 0, validSubTargets = HasV4SubT, addrMode = BaseImmOffset,
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InputType = "imm", isCodeGenOnly = 0 in {
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let accessSize = ByteAccess in
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defm STrib_imm : ST_Imm<"memb", "STrib", u6_0Imm>, ImmRegRel, PredNewRel;
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defm S4_storeirb : ST_Imm<"memb", "STrib", u6_0Imm, 0b00>;
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let accessSize = HalfWordAccess in
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defm STrih_imm : ST_Imm<"memh", "STrih", u6_1Imm>, ImmRegRel, PredNewRel;
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defm S4_storeirh : ST_Imm<"memh", "STrih", u6_1Imm, 0b01>;
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let accessSize = WordAccess in
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defm STriw_imm : ST_Imm<"memw", "STriw", u6_2Imm>, ImmRegRel, PredNewRel;
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defm S4_storeiri : ST_Imm<"memw", "STriw", u6_2Imm, 0b10>;
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}
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let Predicates = [HasV4T], AddedComplexity = 10 in {
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def: Pat<(truncstorei8 s8ExtPred:$src3, (add IntRegs:$src1, u6_0ImmPred:$src2)),
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(STrib_imm_V4 IntRegs:$src1, u6_0ImmPred:$src2, s8ExtPred:$src3)>;
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(S4_storeirb_io IntRegs:$src1, u6_0ImmPred:$src2, s8ExtPred:$src3)>;
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def: Pat<(truncstorei16 s8ExtPred:$src3, (add IntRegs:$src1,
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u6_1ImmPred:$src2)),
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(STrih_imm_V4 IntRegs:$src1, u6_1ImmPred:$src2, s8ExtPred:$src3)>;
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(S4_storeirh_io IntRegs:$src1, u6_1ImmPred:$src2, s8ExtPred:$src3)>;
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def: Pat<(store s8ExtPred:$src3, (add IntRegs:$src1, u6_2ImmPred:$src2)),
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(STriw_imm_V4 IntRegs:$src1, u6_2ImmPred:$src2, s8ExtPred:$src3)>;
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(S4_storeiri_io IntRegs:$src1, u6_2ImmPred:$src2, s8ExtPred:$src3)>;
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}
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let AddedComplexity = 6 in
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def : Pat <(truncstorei8 s8ExtPred:$src2, (i32 IntRegs:$src1)),
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(STrib_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
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(S4_storeirb_io IntRegs:$src1, 0, s8ExtPred:$src2)>,
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Requires<[HasV4T]>;
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// memb(Rx++#s4:0:circ(Mu))=Rt
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@ -990,7 +1039,7 @@ def : Pat <(truncstorei8 s8ExtPred:$src2, (i32 IntRegs:$src1)),
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// memh(Rs+#s11:1)=Rt.H
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let AddedComplexity = 6 in
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def : Pat <(truncstorei16 s8ExtPred:$src2, (i32 IntRegs:$src1)),
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(STrih_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
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(S4_storeirh_io IntRegs:$src1, 0, s8ExtPred:$src2)>,
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Requires<[HasV4T]>;
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// memh(Rs+Ru<<#u2)=Rt.H
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@ -1030,7 +1079,7 @@ def STriw_pred_V4 : STInst2<(outs),
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let AddedComplexity = 6 in
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def : Pat <(store s8ExtPred:$src2, (i32 IntRegs:$src1)),
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(STriw_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
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(S4_storeiri_io IntRegs:$src1, 0, s8ExtPred:$src2)>,
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Requires<[HasV4T]>;
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// memw(Rx++#s4:2)=Rt
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@ -47,6 +47,8 @@
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0x9f 0xf5 0x11 0x3b
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# CHECK: memb(r17 + r21<<#3) = r31
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0x9f 0xca 0x11 0x3c
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# CHECK: memb(r17+#21)=#31
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0x15 0xd5 0x11 0xa1
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# CHECK: memb(r17+#21) = r21
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0x02 0xf5 0x11 0xa9
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@ -69,6 +71,16 @@
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0x03 0x40 0x45 0x85 0xff 0xf5 0x11 0x37
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# CHECK: p3 = r5
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# CHECK-NEXT: if (!p3.new) memb(r17+r21<<#3) = r31
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0xff 0xca 0x11 0x38
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# CHECK: if (p3) memb(r17+#21)=#31
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0xff 0xca 0x91 0x38
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# CHECK: if (!p3) memb(r17+#21)=#31
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0x03 0x40 0x45 0x85 0xff 0xca 0x11 0x39
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# CHECK: p3 = r5
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# CHECK-NEXT: if (p3.new) memb(r17+#21)=#31
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0x03 0x40 0x45 0x85 0xff 0xca 0x91 0x39
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# CHECK: p3 = r5
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# CHECK-NEXT: if (!p3.new) memb(r17+#21)=#31
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0xab 0xdf 0x11 0x40
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# CHECK: if (p3) memb(r17+#21) = r31
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0xab 0xdf 0x11 0x44
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@ -94,6 +106,8 @@
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# CHECK: memh(r17 + r21<<#3) = r31
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0x9f 0xf5 0x71 0x3b
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# CHECK: memh(r17 + r21<<#3) = r31.h
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0x95 0xcf 0x31 0x3c
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# CHECK: memh(r17+#62)=#21
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0x15 0xdf 0x51 0xa1
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# CHECK: memh(r17+#42) = r31
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0x15 0xdf 0x71 0xa1
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@ -138,6 +152,16 @@
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0x03 0x40 0x45 0x85 0xff 0xf5 0x71 0x37
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# CHECK: p3 = r5
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# CHECK-NEXT: if (!p3.new) memh(r17+r21<<#3) = r31.h
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0xf5 0xcf 0x31 0x38
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# CHECK: if (p3) memh(r17+#62)=#21
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0xf5 0xcf 0xb1 0x38
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# CHECK: if (!p3) memh(r17+#62)=#21
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0x03 0x40 0x45 0x85 0xf5 0xcf 0x31 0x39
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# CHECK: p3 = r5
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# CHECK-NEXT: if (p3.new) memh(r17+#62)=#21
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0x03 0x40 0x45 0x85 0xf5 0xcf 0xb1 0x39
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# CHECK: p3 = r5
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# CHECK-NEXT: if (!p3.new) memh(r17+#62)=#21
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0xfb 0xd5 0x51 0x40
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# CHECK: if (p3) memh(r17+#62) = r21
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0xfb 0xd5 0x71 0x40
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@ -181,6 +205,8 @@
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0x9f 0xf5 0x91 0x3b
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# CHECK: memw(r17 + r21<<#3) = r31
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0x9f 0xca 0x51 0x3c
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# CHECK: memw(r17+#84)=#31
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0x15 0xdf 0x91 0xa1
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# CHECK: memw(r17+#84) = r31
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0x02 0xf5 0x91 0xa9
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@ -203,6 +229,16 @@
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0x03 0x40 0x45 0x85 0xff 0xf5 0x91 0x37
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# CHECK: p3 = r5
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# CHECK-NEXT: if (!p3.new) memw(r17+r21<<#3) = r31
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0xff 0xca 0x51 0x38
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# CHECK: if (p3) memw(r17+#84)=#31
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0xff 0xca 0xd1 0x38
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# CHECK: if (!p3) memw(r17+#84)=#31
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0x03 0x40 0x45 0x85 0xff 0xca 0x51 0x39
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# CHECK: p3 = r5
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# CHECK-NEXT: if (p3.new) memw(r17+#84)=#31
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0x03 0x40 0x45 0x85 0xff 0xca 0xd1 0x39
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# CHECK: p3 = r5
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# CHECK-NEXT: if (!p3.new) memw(r17+#84)=#31
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0xab 0xdf 0x91 0x40
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# CHECK: if (p3) memw(r17+#84) = r31
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0xab 0xdf 0x91 0x44
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