mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
[PowerPC] Add fast-isel branch and compare selection.
First chunk of actual fast-isel selection code. This handles direct and indirect branches, as well as feeding compares for direct branches. PPCFastISel::PPCEmitIntExt() is just roughed in and will be expanded in a future patch. This also corrects a problem with selection for constant pool entries in JIT mode or with small code model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189202 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Schmidt
parent
a4959f3f6e
commit
3fad2bcd25
@ -89,9 +89,19 @@ class PPCFastISel : public FastISel {
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virtual bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
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const LoadInst *LI);
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virtual bool FastLowerArguments();
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virtual unsigned FastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm);
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// Instruction selection routines.
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private:
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bool SelectBranch(const Instruction *I);
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bool SelectIndirectBr(const Instruction *I);
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// Utility routines.
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private:
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bool PPCEmitCmp(const Value *Src1Value, const Value *Src2Value,
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bool isZExt, unsigned DestReg);
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bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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unsigned DestReg, bool IsZExt);
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unsigned PPCMaterializeFP(const ConstantFP *CFP, MVT VT);
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unsigned PPCMaterializeInt(const Constant *C, MVT VT);
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unsigned PPCMaterialize32BitInt(int64_t Imm,
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@ -106,10 +116,241 @@ class PPCFastISel : public FastISel {
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} // end anonymous namespace
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static Optional<PPC::Predicate> getComparePred(CmpInst::Predicate Pred) {
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switch (Pred) {
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// These are not representable with any single compare.
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case CmpInst::FCMP_FALSE:
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case CmpInst::FCMP_UEQ:
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case CmpInst::FCMP_UGT:
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case CmpInst::FCMP_UGE:
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case CmpInst::FCMP_ULT:
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case CmpInst::FCMP_ULE:
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case CmpInst::FCMP_UNE:
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case CmpInst::FCMP_TRUE:
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default:
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return Optional<PPC::Predicate>();
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case CmpInst::FCMP_OEQ:
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case CmpInst::ICMP_EQ:
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return PPC::PRED_EQ;
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case CmpInst::FCMP_OGT:
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case CmpInst::ICMP_UGT:
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case CmpInst::ICMP_SGT:
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return PPC::PRED_GT;
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case CmpInst::FCMP_OGE:
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case CmpInst::ICMP_UGE:
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case CmpInst::ICMP_SGE:
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return PPC::PRED_GE;
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case CmpInst::FCMP_OLT:
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case CmpInst::ICMP_ULT:
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case CmpInst::ICMP_SLT:
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return PPC::PRED_LT;
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case CmpInst::FCMP_OLE:
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case CmpInst::ICMP_ULE:
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case CmpInst::ICMP_SLE:
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return PPC::PRED_LE;
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case CmpInst::FCMP_ONE:
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case CmpInst::ICMP_NE:
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return PPC::PRED_NE;
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case CmpInst::FCMP_ORD:
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return PPC::PRED_NU;
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case CmpInst::FCMP_UNO:
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return PPC::PRED_UN;
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}
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}
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// Attempt to fast-select a branch instruction.
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bool PPCFastISel::SelectBranch(const Instruction *I) {
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const BranchInst *BI = cast<BranchInst>(I);
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MachineBasicBlock *BrBB = FuncInfo.MBB;
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MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
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MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
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// For now, just try the simplest case where it's fed by a compare.
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if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
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Optional<PPC::Predicate> OptPPCPred = getComparePred(CI->getPredicate());
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if (!OptPPCPred)
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return false;
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PPC::Predicate PPCPred = OptPPCPred.getValue();
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// Take advantage of fall-through opportunities.
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if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
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std::swap(TBB, FBB);
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PPCPred = PPC::InvertPredicate(PPCPred);
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}
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unsigned CondReg = createResultReg(&PPC::CRRCRegClass);
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if (!PPCEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(),
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CondReg))
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return false;
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BuildMI(*BrBB, FuncInfo.InsertPt, DL, TII.get(PPC::BCC))
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.addImm(PPCPred).addReg(CondReg).addMBB(TBB);
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FastEmitBranch(FBB, DL);
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FuncInfo.MBB->addSuccessor(TBB);
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return true;
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} else if (const ConstantInt *CI =
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dyn_cast<ConstantInt>(BI->getCondition())) {
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uint64_t Imm = CI->getZExtValue();
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MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
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FastEmitBranch(Target, DL);
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return true;
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}
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// FIXME: ARM looks for a case where the block containing the compare
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// has been split from the block containing the branch. If this happens,
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// there is a vreg available containing the result of the compare. I'm
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// not sure we can do much, as we've lost the predicate information with
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// the compare instruction -- we have a 4-bit CR but don't know which bit
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// to test here.
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return false;
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}
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// Attempt to emit a compare of the two source values. Signed and unsigned
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// comparisons are supported. Return false if we can't handle it.
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bool PPCFastISel::PPCEmitCmp(const Value *SrcValue1, const Value *SrcValue2,
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bool IsZExt, unsigned DestReg) {
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Type *Ty = SrcValue1->getType();
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EVT SrcEVT = TLI.getValueType(Ty, true);
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if (!SrcEVT.isSimple())
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return false;
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MVT SrcVT = SrcEVT.getSimpleVT();
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// See if operand 2 is an immediate encodeable in the compare.
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// FIXME: Operands are not in canonical order at -O0, so an immediate
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// operand in position 1 is a lost opportunity for now. We are
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// similar to ARM in this regard.
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long Imm = 0;
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bool UseImm = false;
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// Only 16-bit integer constants can be represented in compares for
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// PowerPC. Others will be materialized into a register.
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if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(SrcValue2)) {
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if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
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SrcVT == MVT::i8 || SrcVT == MVT::i1) {
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const APInt &CIVal = ConstInt->getValue();
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Imm = (IsZExt) ? (long)CIVal.getZExtValue() : (long)CIVal.getSExtValue();
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if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm)))
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UseImm = true;
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}
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}
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unsigned CmpOpc;
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bool NeedsExt = false;
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switch (SrcVT.SimpleTy) {
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default: return false;
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case MVT::f32:
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CmpOpc = PPC::FCMPUS;
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break;
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case MVT::f64:
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CmpOpc = PPC::FCMPUD;
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break;
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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NeedsExt = true;
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// Intentional fall-through.
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case MVT::i32:
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if (!UseImm)
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CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW;
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else
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CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI;
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break;
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case MVT::i64:
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if (!UseImm)
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CmpOpc = IsZExt ? PPC::CMPLD : PPC::CMPD;
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else
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CmpOpc = IsZExt ? PPC::CMPLDI : PPC::CMPDI;
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break;
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}
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unsigned SrcReg1 = getRegForValue(SrcValue1);
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if (SrcReg1 == 0)
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return false;
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unsigned SrcReg2 = 0;
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if (!UseImm) {
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SrcReg2 = getRegForValue(SrcValue2);
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if (SrcReg2 == 0)
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return false;
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}
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if (NeedsExt) {
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unsigned ExtReg = createResultReg(&PPC::GPRCRegClass);
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if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt))
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return false;
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SrcReg1 = ExtReg;
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if (!UseImm) {
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unsigned ExtReg = createResultReg(&PPC::GPRCRegClass);
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if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt))
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return false;
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SrcReg2 = ExtReg;
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}
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}
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if (!UseImm)
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc), DestReg)
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.addReg(SrcReg1).addReg(SrcReg2);
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else
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc), DestReg)
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.addReg(SrcReg1).addImm(Imm);
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return true;
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}
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// Attempt to emit an integer extend of SrcReg into DestReg. Both
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// signed and zero extensions are supported. Return false if we
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// can't handle it. Not yet implemented.
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bool PPCFastISel::PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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unsigned DestReg, bool IsZExt) {
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return (SrcVT == MVT::i8 && SrcReg && DestVT == MVT::i8 && DestReg
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&& IsZExt && false);
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}
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// Attempt to fast-select an indirect branch instruction.
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bool PPCFastISel::SelectIndirectBr(const Instruction *I) {
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unsigned AddrReg = getRegForValue(I->getOperand(0));
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if (AddrReg == 0)
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return false;
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::MTCTR8))
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.addReg(AddrReg);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::BCTR8));
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const IndirectBrInst *IB = cast<IndirectBrInst>(I);
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for (unsigned i = 0, e = IB->getNumSuccessors(); i != e; ++i)
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FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[IB->getSuccessor(i)]);
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return true;
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}
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// Attempt to fast-select an instruction that wasn't handled by
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// the table-generated machinery. TBD.
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// the table-generated machinery.
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bool PPCFastISel::TargetSelectInstruction(const Instruction *I) {
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return I && false;
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switch (I->getOpcode()) {
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case Instruction::Br:
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return SelectBranch(I);
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case Instruction::IndirectBr:
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return SelectIndirectBr(I);
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// Here add other flavors of Instruction::XXX that automated
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// cases don't catch. For example, switches are terminators
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// that aren't yet handled.
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default:
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break;
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}
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return false;
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}
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// Materialize a floating-point constant into a register, and return
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@ -131,15 +372,18 @@ unsigned PPCFastISel::PPCMaterializeFP(const ConstantFP *CFP, MVT VT) {
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MachinePointerInfo::getConstantPool(), MachineMemOperand::MOLoad,
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(VT == MVT::f32) ? 4 : 8, Align);
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// For small code model, generate a LDtocCPT.
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if (CModel == CodeModel::Small || CModel == CodeModel::JITDefault)
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unsigned Opc = (VT == MVT::f32) ? PPC::LFS : PPC::LFD;
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unsigned TmpReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
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// For small code model, generate a LF[SD](0, LDtocCPT(Idx, X2)).
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if (CModel == CodeModel::Small || CModel == CodeModel::JITDefault) {
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::LDtocCPT),
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DestReg)
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.addConstantPoolIndex(Idx).addReg(PPC::X2).addMemOperand(MMO);
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else {
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TmpReg)
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.addConstantPoolIndex(Idx).addReg(PPC::X2);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
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.addImm(0).addReg(TmpReg).addMemOperand(MMO);
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} else {
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// Otherwise we generate LF[SD](Idx[lo], ADDIStocHA(X2, Idx)).
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unsigned Opc = (VT == MVT::f32) ? PPC::LFS : PPC::LFD;
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unsigned TmpReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::ADDIStocHA),
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TmpReg).addReg(PPC::X2).addConstantPoolIndex(Idx);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
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@ -312,6 +556,25 @@ bool PPCFastISel::FastLowerArguments() {
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return false;
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}
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// Handle materializing integer constants into a register. This is not
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// automatically generated for PowerPC, so must be explicitly created here.
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unsigned PPCFastISel::FastEmit_i(MVT Ty, MVT VT, unsigned Opc, uint64_t Imm) {
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if (Opc != ISD::Constant)
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return 0;
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if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 &&
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VT != MVT::i8 && VT != MVT::i1)
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return 0;
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const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass :
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&PPC::GPRCRegClass);
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if (VT == MVT::i64)
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return PPCMaterialize64BitInt(Imm, RC);
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else
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return PPCMaterialize32BitInt(Imm, RC);
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}
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namespace llvm {
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// Create the fast instruction selector for PowerPC64 ELF.
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FastISel *PPC::createFastISel(FunctionLoweringInfo &FuncInfo,
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43
test/CodeGen/PowerPC/fast-isel-br-const.ll
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43
test/CodeGen/PowerPC/fast-isel-br-const.ll
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@ -0,0 +1,43 @@
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
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define i32 @t1(i32 %a, i32 %b) nounwind uwtable ssp {
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entry:
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; ELF64: t1
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%x = add i32 %a, %b
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br i1 1, label %if.then, label %if.else
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; ELF64-NOT: b {{\.?}}LBB0_1
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if.then: ; preds = %entry
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call void @foo1()
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br label %if.end7
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if.else: ; preds = %entry
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br i1 0, label %if.then2, label %if.else3
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; ELF64: b {{\.?}}LBB0_4
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if.then2: ; preds = %if.else
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call void @foo2()
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br label %if.end6
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if.else3: ; preds = %if.else
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%y = sub i32 %a, %b
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br i1 1, label %if.then5, label %if.end
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; ELF64-NOT: b {{\.?}}LBB0_5
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if.then5: ; preds = %if.else3
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call void @foo1()
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br label %if.end
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if.end: ; preds = %if.then5, %if.else3
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br label %if.end6
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if.end6: ; preds = %if.end, %if.then2
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br label %if.end7
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if.end7: ; preds = %if.end6, %if.then
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ret i32 0
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}
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declare void @foo1()
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declare void @foo2()
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15
test/CodeGen/PowerPC/fast-isel-indirectbr.ll
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15
test/CodeGen/PowerPC/fast-isel-indirectbr.ll
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@ -0,0 +1,15 @@
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
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define void @t1(i8* %x) {
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entry:
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; ELF64: t1
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br label %L0
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L0:
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br label %L1
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L1:
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indirectbr i8* %x, [ label %L0, label %L1 ]
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; ELF64: mtctr 3
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; ELF64: bctr
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}
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