6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-19 04:32:19 +00:00
Code Issues Projects Releases Wiki Activity

make the vector conversion magic handle multiple results.

Browse Source 
We now compile test2/test3 to:

_test2:
	## InlineAsm Start
	set %xmm0, %xmm1
	## InlineAsm End
	addps	%xmm1, %xmm0
	ret
_test3:
	## InlineAsm Start
	set %xmm0, %xmm1
	## InlineAsm End
	paddd	%xmm1, %xmm0
	ret

as expected.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50389 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2008-04-29 04:48:56 +00:00
parent 41f6259a4b
commit 3fb2968f2f
2 changed files with 36 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -4119,15 +4119,24 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
// and set it as the value of the call.
if (!RetValRegs.Regs.empty()) {
SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
// If the result of the inline asm is a vector, it may have the wrong
// width/num elts. Make sure to convert it to the right type with
// If any of the results of the inline asm is a vector, it may have the
// wrong width/num elts. This can happen for register classes that can
// contain multiple different value types. The preg or vreg allocated may
// not have the same VT as was expected. Convert it to the right type with
// bit_convert.
if (MVT::isVector(Val.getValueType())) {
MVT::ValueType DesiredVT = TLI.getValueType(CS.getType());
Val = DAG.getNode(ISD::BIT_CONVERT, DesiredVT, Val);
if (const StructType *ResSTy = dyn_cast<StructType>(CS.getType())) {
for (unsigned i = 0, e = ResSTy->getNumElements(); i != e; ++i) {
if (MVT::isVector(Val.Val->getValueType(i)))
Val = DAG.getNode(ISD::BIT_CONVERT,
TLI.getValueType(ResSTy->getElementType(i)), Val);
}
} else {
if (MVT::isVector(Val.getValueType()))
Val = DAG.getNode(ISD::BIT_CONVERT, TLI.getValueType(CS.getType()),
Val);
}
setValue(CS.getInstruction(), Val);
}

22
test/CodeGen/X86/inline-asm-mrv.ll
View File

@ -1,12 +1,13 @@
; PR2094
; RUN: llvm-as < %s | llc -march=x86-64 | grep movslq
; RUN: llvm-as < %s | llc -march=x86-64 | grep addps
; RUN: llvm-as < %s | llc -march=x86-64 | grep paddd
; RUN: llvm-as < %s | llc -march=x86-64 | not grep movq
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-apple-darwin8"
define i32 @sad16_sse2(i8* %v, i8* %blk2, i8* %blk1, i32 %stride, i32 %h) nounwind {
entry:
define i32 @test1(i8* %v, i8* %blk2, i8* %blk1, i32 %stride, i32 %h) nounwind {
%tmp12 = sext i32 %stride to i64 ; <i64> [#uses=1]
%mrv = call {i32, i8*, i8*} asm sideeffect "$0 $1 $2 $3 $4 $5 $6",
"=r,=r,=r,r,r,r,r"( i64 %tmp12, i32 %h, i8* %blk1, i8* %blk2 ) nounwind
@ -15,3 +16,20 @@ entry:
"=r,~{dirflag},~{fpsr},~{flags}"( ) nounwind
ret i32 %tmp7
}
define <4 x float> @test2() nounwind {
%mrv = call {<4 x float>, <4 x float>} asm "set $0, $1", "=x,=x"()
%a = getresult {<4 x float>, <4 x float>} %mrv, 0
%b = getresult {<4 x float>, <4 x float>} %mrv, 1
%c = add <4 x float> %a, %b
ret <4 x float> %c
}
define <4 x i32> @test3() nounwind {
%mrv = call {<4 x i32>, <4 x i32>} asm "set $0, $1", "=x,=x"()
%a = getresult {<4 x i32>, <4 x i32>} %mrv, 0
%b = getresult {<4 x i32>, <4 x i32>} %mrv, 1
%c = add <4 x i32> %a, %b
ret <4 x i32> %c
}