mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-22 10:29:35 +00:00
Implement AArch64 Neon Crypto instruction classes AES, SHA, and 3 SHA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194085 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jiangning Liu
parent
e05744ba85
commit
3ff3a8aa75
@ -271,4 +271,12 @@ def int_aarch64_neon_vcvtf32_n_u32 :
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Intrinsic<[llvm_v1f32_ty], [llvm_v1i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_aarch64_neon_vcvtf64_n_u64 :
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Intrinsic<[llvm_v1f64_ty], [llvm_v1i64_ty, llvm_i32_ty], [IntrNoMem]>;
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class Neon_SHA_Intrinsic
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: Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v1i32_ty, llvm_v4i32_ty],
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[IntrNoMem]>;
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def int_aarch64_neon_sha1c : Neon_SHA_Intrinsic;
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def int_aarch64_neon_sha1m : Neon_SHA_Intrinsic;
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def int_aarch64_neon_sha1p : Neon_SHA_Intrinsic;
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}
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@ -1279,5 +1279,49 @@ class NeonI_ScalarShiftImm<bit u, bits<5> opcode,
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// Inherit Rd in 4-0
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}
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// Format AdvSIMD crypto AES
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class NeonI_Crypto_AES<bits<2> size, bits<5> opcode,
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dag outs, dag ins, string asmstr,
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list<dag> patterns, InstrItinClass itin>
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: A64InstRdn<outs, ins, asmstr, patterns, itin> {
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let Inst{31-24} = 0b01001110;
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let Inst{23-22} = size;
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let Inst{21-17} = 0b10100;
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let Inst{16-12} = opcode;
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let Inst{11-10} = 0b10;
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// Inherit Rn in 9-5
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// Inherit Rd in 4-0
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}
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// Format AdvSIMD crypto SHA
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class NeonI_Crypto_SHA<bits<2> size, bits<5> opcode,
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dag outs, dag ins, string asmstr,
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list<dag> patterns, InstrItinClass itin>
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: A64InstRdn<outs, ins, asmstr, patterns, itin> {
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let Inst{31-24} = 0b01011110;
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let Inst{23-22} = size;
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let Inst{21-17} = 0b10100;
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let Inst{16-12} = opcode;
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let Inst{11-10} = 0b10;
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// Inherit Rn in 9-5
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// Inherit Rd in 4-0
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}
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// Format AdvSIMD crypto 3V SHA
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class NeonI_Crypto_3VSHA<bits<2> size, bits<3> opcode,
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dag outs, dag ins, string asmstr,
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list<dag> patterns, InstrItinClass itin>
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: A64InstRdnm<outs, ins, asmstr, patterns, itin> {
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let Inst{31-24} = 0b01011110;
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let Inst{23-22} = size;
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let Inst{21} = 0b0;
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// Inherit Rm in 20-16
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let Inst{15} = 0b0;
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let Inst{14-12} = opcode;
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let Inst{11-10} = 0b00;
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// Inherit Rn in 9-5
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// Inherit Rd in 4-0
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}
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}
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@ -2663,11 +2663,14 @@ defm UABDLvvv : NeonI_3VDL_zext<0b1, 0b0111, "uabdl", int_arm_neon_vabdu, 1>;
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multiclass NeonI_Op_High<SDPatternOperator op> {
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def _16B : PatFrag<(ops node:$Rn, node:$Rm),
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(op (v8i8 (Neon_High16B node:$Rn)), (v8i8 (Neon_High16B node:$Rm)))>;
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(op (v8i8 (Neon_High16B node:$Rn)),
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(v8i8 (Neon_High16B node:$Rm)))>;
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def _8H : PatFrag<(ops node:$Rn, node:$Rm),
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(op (v4i16 (Neon_High8H node:$Rn)), (v4i16 (Neon_High8H node:$Rm)))>;
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(op (v4i16 (Neon_High8H node:$Rn)),
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(v4i16 (Neon_High8H node:$Rm)))>;
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def _4S : PatFrag<(ops node:$Rn, node:$Rm),
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(op (v2i32 (Neon_High4S node:$Rn)), (v2i32 (Neon_High4S node:$Rm)))>;
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(op (v2i32 (Neon_High4S node:$Rn)),
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(v2i32 (Neon_High4S node:$Rm)))>;
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}
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defm NI_sabdl_hi : NeonI_Op_High<int_arm_neon_vabds>;
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@ -5793,3 +5796,116 @@ def : Pat<(v2f32 (extract_subvector (v4f32 VPR128:$Rn), (i64 0))),
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(v2f32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
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def : Pat<(v1f64 (extract_subvector (v2f64 VPR128:$Rn), (i64 0))),
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(v1f64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
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// Crypto Class
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class NeonI_Cryptoaes_2v<bits<2> size, bits<5> opcode,
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string asmop, SDPatternOperator opnode>
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: NeonI_Crypto_AES<size, opcode,
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(outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
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asmop # "\t$Rd.16b, $Rn.16b",
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[(set (v16i8 VPR128:$Rd),
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(v16i8 (opnode (v16i8 VPR128:$src),
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(v16i8 VPR128:$Rn))))],
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NoItinerary>{
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let Constraints = "$src = $Rd";
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}
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def AESE : NeonI_Cryptoaes_2v<0b00, 0b00100, "aese", int_arm_neon_aese>;
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def AESD : NeonI_Cryptoaes_2v<0b00, 0b00101, "aesd", int_arm_neon_aesd>;
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class NeonI_Cryptoaes<bits<2> size, bits<5> opcode,
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string asmop, SDPatternOperator opnode>
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: NeonI_Crypto_AES<size, opcode,
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(outs VPR128:$Rd), (ins VPR128:$Rn),
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asmop # "\t$Rd.16b, $Rn.16b",
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[(set (v16i8 VPR128:$Rd),
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(v16i8 (opnode (v16i8 VPR128:$Rn))))],
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NoItinerary>;
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def AESMC : NeonI_Cryptoaes<0b00, 0b00110, "aesmc", int_arm_neon_aesmc>;
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def AESIMC : NeonI_Cryptoaes<0b00, 0b00111, "aesimc", int_arm_neon_aesimc>;
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class NeonI_Cryptosha_vv<bits<2> size, bits<5> opcode,
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string asmop, SDPatternOperator opnode>
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: NeonI_Crypto_SHA<size, opcode,
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(outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
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asmop # "\t$Rd.4s, $Rn.4s",
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[(set (v4i32 VPR128:$Rd),
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(v4i32 (opnode (v4i32 VPR128:$src),
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(v4i32 VPR128:$Rn))))],
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NoItinerary> {
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let Constraints = "$src = $Rd";
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}
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def SHA1SU1 : NeonI_Cryptosha_vv<0b00, 0b00001, "sha1su1",
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int_arm_neon_sha1su1>;
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def SHA256SU0 : NeonI_Cryptosha_vv<0b00, 0b00010, "sha256su0",
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int_arm_neon_sha256su0>;
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class NeonI_Cryptosha_ss<bits<2> size, bits<5> opcode,
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string asmop, SDPatternOperator opnode>
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: NeonI_Crypto_SHA<size, opcode,
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(outs FPR32:$Rd), (ins FPR32:$Rn),
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asmop # "\t$Rd, $Rn",
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[(set (v1i32 FPR32:$Rd),
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(v1i32 (opnode (v1i32 FPR32:$Rn))))],
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NoItinerary>;
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def SHA1H : NeonI_Cryptosha_ss<0b00, 0b00000, "sha1h", int_arm_neon_sha1h>;
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class NeonI_Cryptosha3_vvv<bits<2> size, bits<3> opcode, string asmop,
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SDPatternOperator opnode>
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: NeonI_Crypto_3VSHA<size, opcode,
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(outs VPR128:$Rd),
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(ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
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asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
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[(set (v4i32 VPR128:$Rd),
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(v4i32 (opnode (v4i32 VPR128:$src),
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(v4i32 VPR128:$Rn),
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(v4i32 VPR128:$Rm))))],
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NoItinerary> {
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let Constraints = "$src = $Rd";
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}
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def SHA1SU0 : NeonI_Cryptosha3_vvv<0b00, 0b011, "sha1su0",
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int_arm_neon_sha1su0>;
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def SHA256SU1 : NeonI_Cryptosha3_vvv<0b00, 0b110, "sha256su1",
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int_arm_neon_sha256su1>;
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class NeonI_Cryptosha3_qqv<bits<2> size, bits<3> opcode, string asmop,
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SDPatternOperator opnode>
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: NeonI_Crypto_3VSHA<size, opcode,
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(outs FPR128:$Rd),
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(ins FPR128:$src, FPR128:$Rn, VPR128:$Rm),
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asmop # "\t$Rd, $Rn, $Rm.4s",
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[(set (v4i32 FPR128:$Rd),
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(v4i32 (opnode (v4i32 FPR128:$src),
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(v4i32 FPR128:$Rn),
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(v4i32 VPR128:$Rm))))],
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NoItinerary> {
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let Constraints = "$src = $Rd";
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}
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def SHA256H : NeonI_Cryptosha3_qqv<0b00, 0b100, "sha256h",
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int_arm_neon_sha256h>;
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def SHA256H2 : NeonI_Cryptosha3_qqv<0b00, 0b101, "sha256h2",
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int_arm_neon_sha256h2>;
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class NeonI_Cryptosha3_qsv<bits<2> size, bits<3> opcode, string asmop,
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SDPatternOperator opnode>
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: NeonI_Crypto_3VSHA<size, opcode,
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(outs FPR128:$Rd),
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(ins FPR128:$src, FPR32:$Rn, VPR128:$Rm),
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asmop # "\t$Rd, $Rn, $Rm.4s",
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[(set (v4i32 FPR128:$Rd),
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(v4i32 (opnode (v4i32 FPR128:$src),
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(v1i32 FPR32:$Rn),
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(v4i32 VPR128:$Rm))))],
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NoItinerary> {
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let Constraints = "$src = $Rd";
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}
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def SHA1C : NeonI_Cryptosha3_qsv<0b00, 0b000, "sha1c", int_aarch64_neon_sha1c>;
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def SHA1P : NeonI_Cryptosha3_qsv<0b00, 0b001, "sha1p", int_aarch64_neon_sha1p>;
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def SHA1M : NeonI_Cryptosha3_qsv<0b00, 0b010, "sha1m", int_aarch64_neon_sha1m>;
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@ -164,7 +164,7 @@ def FPR64 : RegisterClass<"AArch64",
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64, (sequence "D%u", 0, 31)>;
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def FPR128 : RegisterClass<"AArch64",
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[f128,v2f64, v2i64, v4f32, v4i32, v8i16, v16i8],
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[f128, v2f64, v2i64, v4f32, v4i32, v8i16, v16i8],
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128, (sequence "Q%u", 0, 31)>;
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def FPR64Lo : RegisterClass<"AArch64",
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@ -172,7 +172,7 @@ def FPR64Lo : RegisterClass<"AArch64",
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64, (sequence "D%u", 0, 15)>;
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def FPR128Lo : RegisterClass<"AArch64",
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[f128,v2f64, v2i64, v4f32, v4i32, v8i16, v16i8],
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[f128, v2f64, v2i64, v4f32, v4i32, v8i16, v16i8],
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128, (sequence "Q%u", 0, 15)>;
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//===----------------------------------------------------------------------===//
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147
test/CodeGen/AArch64/neon-crypto.ll
Normal file
147
test/CodeGen/AArch64/neon-crypto.ll
Normal file
@ -0,0 +1,147 @@
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; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
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declare <4 x i32> @llvm.arm.neon.sha256su1.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) #1
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declare <4 x i32> @llvm.arm.neon.sha256h2.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) #1
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declare <4 x i32> @llvm.arm.neon.sha256h.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) #1
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declare <4 x i32> @llvm.arm.neon.sha1su0.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) #1
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declare <4 x i32> @llvm.aarch64.neon.sha1m(<4 x i32>, <1 x i32>, <4 x i32>) #1
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declare <4 x i32> @llvm.aarch64.neon.sha1p(<4 x i32>, <1 x i32>, <4 x i32>) #1
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declare <4 x i32> @llvm.aarch64.neon.sha1c(<4 x i32>, <1 x i32>, <4 x i32>) #1
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declare <4 x i32> @llvm.arm.neon.sha256su0.v4i32(<4 x i32>, <4 x i32>) #1
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declare <4 x i32> @llvm.arm.neon.sha1su1.v4i32(<4 x i32>, <4 x i32>) #1
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declare <1 x i32> @llvm.arm.neon.sha1h.v1i32(<1 x i32>) #1
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declare <16 x i8> @llvm.arm.neon.aesimc.v16i8(<16 x i8>) #1
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declare <16 x i8> @llvm.arm.neon.aesmc.v16i8(<16 x i8>) #1
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declare <16 x i8> @llvm.arm.neon.aesd.v16i8(<16 x i8>, <16 x i8>) #1
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declare <16 x i8> @llvm.arm.neon.aese.v16i8(<16 x i8>, <16 x i8>) #1
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define <16 x i8> @test_vaeseq_u8(<16 x i8> %data, <16 x i8> %key) {
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; CHECK: test_vaeseq_u8:
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; CHECK: aese {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
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entry:
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%aese.i = tail call <16 x i8> @llvm.arm.neon.aese.v16i8(<16 x i8> %data, <16 x i8> %key)
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ret <16 x i8> %aese.i
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}
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define <16 x i8> @test_vaesdq_u8(<16 x i8> %data, <16 x i8> %key) {
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; CHECK: test_vaesdq_u8:
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; CHECK: aesd {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
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entry:
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%aesd.i = tail call <16 x i8> @llvm.arm.neon.aesd.v16i8(<16 x i8> %data, <16 x i8> %key)
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ret <16 x i8> %aesd.i
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}
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define <16 x i8> @test_vaesmcq_u8(<16 x i8> %data) {
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; CHECK: test_vaesmcq_u8:
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; CHECK: aesmc {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
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entry:
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%aesmc.i = tail call <16 x i8> @llvm.arm.neon.aesmc.v16i8(<16 x i8> %data)
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ret <16 x i8> %aesmc.i
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}
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define <16 x i8> @test_vaesimcq_u8(<16 x i8> %data) {
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; CHECK: test_vaesimcq_u8:
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; CHECK: aesimc {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
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entry:
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%aesimc.i = tail call <16 x i8> @llvm.arm.neon.aesimc.v16i8(<16 x i8> %data)
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ret <16 x i8> %aesimc.i
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}
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define i32 @test_vsha1h_u32(i32 %hash_e) {
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; CHECK: test_vsha1h_u32:
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; CHECK: sha1h {{s[0-9]+}}, {{s[0-9]+}}
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entry:
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%sha1h.i = insertelement <1 x i32> undef, i32 %hash_e, i32 0
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%sha1h1.i = tail call <1 x i32> @llvm.arm.neon.sha1h.v1i32(<1 x i32> %sha1h.i)
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%0 = extractelement <1 x i32> %sha1h1.i, i32 0
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ret i32 %0
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}
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define <4 x i32> @test_vsha1su1q_u32(<4 x i32> %tw0_3, <4 x i32> %w12_15) {
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; CHECK: test_vsha1su1q_u32:
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; CHECK: sha1su1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
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entry:
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%sha1su12.i = tail call <4 x i32> @llvm.arm.neon.sha1su1.v4i32(<4 x i32> %tw0_3, <4 x i32> %w12_15)
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ret <4 x i32> %sha1su12.i
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}
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define <4 x i32> @test_vsha256su0q_u32(<4 x i32> %w0_3, <4 x i32> %w4_7) {
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; CHECK: test_vsha256su0q_u32:
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; CHECK: sha256su0 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
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entry:
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%sha256su02.i = tail call <4 x i32> @llvm.arm.neon.sha256su0.v4i32(<4 x i32> %w0_3, <4 x i32> %w4_7)
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ret <4 x i32> %sha256su02.i
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}
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define <4 x i32> @test_vsha1cq_u32(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
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; CHECK: test_vsha1cq_u32:
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; CHECK: sha1c {{q[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.4s
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entry:
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%sha1c.i = insertelement <1 x i32> undef, i32 %hash_e, i32 0
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%sha1c1.i = tail call <4 x i32> @llvm.aarch64.neon.sha1c(<4 x i32> %hash_abcd, <1 x i32> %sha1c.i, <4 x i32> %wk)
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ret <4 x i32> %sha1c1.i
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}
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define <4 x i32> @test_vsha1pq_u32(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
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; CHECK: test_vsha1pq_u32:
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; CHECK: sha1p {{q[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.4s
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entry:
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%sha1p.i = insertelement <1 x i32> undef, i32 %hash_e, i32 0
|
||||
%sha1p1.i = tail call <4 x i32> @llvm.aarch64.neon.sha1p(<4 x i32> %hash_abcd, <1 x i32> %sha1p.i, <4 x i32> %wk)
|
||||
ret <4 x i32> %sha1p1.i
|
||||
}
|
||||
|
||||
define <4 x i32> @test_vsha1mq_u32(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
|
||||
; CHECK: test_vsha1mq_u32:
|
||||
; CHECK: sha1m {{q[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.4s
|
||||
entry:
|
||||
%sha1m.i = insertelement <1 x i32> undef, i32 %hash_e, i32 0
|
||||
%sha1m1.i = tail call <4 x i32> @llvm.aarch64.neon.sha1m(<4 x i32> %hash_abcd, <1 x i32> %sha1m.i, <4 x i32> %wk)
|
||||
ret <4 x i32> %sha1m1.i
|
||||
}
|
||||
|
||||
define <4 x i32> @test_vsha1su0q_u32(<4 x i32> %w0_3, <4 x i32> %w4_7, <4 x i32> %w8_11) {
|
||||
; CHECK: test_vsha1su0q_u32:
|
||||
; CHECK: sha1su0 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
|
||||
entry:
|
||||
%sha1su03.i = tail call <4 x i32> @llvm.arm.neon.sha1su0.v4i32(<4 x i32> %w0_3, <4 x i32> %w4_7, <4 x i32> %w8_11)
|
||||
ret <4 x i32> %sha1su03.i
|
||||
}
|
||||
|
||||
define <4 x i32> @test_vsha256hq_u32(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk) {
|
||||
; CHECK: test_vsha256hq_u32:
|
||||
; CHECK: sha256h {{q[0-9]+}}, {{q[0-9]+}}, {{v[0-9]+}}.4s
|
||||
entry:
|
||||
%sha256h3.i = tail call <4 x i32> @llvm.arm.neon.sha256h.v4i32(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk)
|
||||
ret <4 x i32> %sha256h3.i
|
||||
}
|
||||
|
||||
define <4 x i32> @test_vsha256h2q_u32(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk) {
|
||||
; CHECK: test_vsha256h2q_u32:
|
||||
; CHECK: sha256h2 {{q[0-9]+}}, {{q[0-9]+}}, {{v[0-9]+}}.4s
|
||||
entry:
|
||||
%sha256h23.i = tail call <4 x i32> @llvm.arm.neon.sha256h2.v4i32(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk)
|
||||
ret <4 x i32> %sha256h23.i
|
||||
}
|
||||
|
||||
define <4 x i32> @test_vsha256su1q_u32(<4 x i32> %tw0_3, <4 x i32> %w8_11, <4 x i32> %w12_15) {
|
||||
; CHECK: test_vsha256su1q_u32:
|
||||
; CHECK: sha256su1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
|
||||
entry:
|
||||
%sha256su13.i = tail call <4 x i32> @llvm.arm.neon.sha256su1.v4i32(<4 x i32> %tw0_3, <4 x i32> %w8_11, <4 x i32> %w12_15)
|
||||
ret <4 x i32> %sha256su13.i
|
||||
}
|
||||
|
||||
42
test/MC/AArch64/neon-crypto.s
Normal file
42
test/MC/AArch64/neon-crypto.s
Normal file
@ -0,0 +1,42 @@
|
||||
// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s
|
||||
|
||||
// Check that the assembler can handle the documented syntax for AArch64
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// Instructions for crypto
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
aese v0.16b, v1.16b
|
||||
aesd v0.16b, v1.16b
|
||||
aesmc v0.16b, v1.16b
|
||||
aesimc v0.16b, v1.16b
|
||||
|
||||
// CHECK: aese v0.16b, v1.16b // encoding: [0x20,0x48,0x28,0x4e]
|
||||
// CHECK: aesd v0.16b, v1.16b // encoding: [0x20,0x58,0x28,0x4e]
|
||||
// CHECK: aesmc v0.16b, v1.16b // encoding: [0x20,0x68,0x28,0x4e]
|
||||
// CHECK: aesimc v0.16b, v1.16b // encoding: [0x20,0x78,0x28,0x4e]
|
||||
|
||||
sha1h s0, s1
|
||||
sha1su1 v0.4s, v1.4s
|
||||
sha256su0 v0.4s, v1.4s
|
||||
|
||||
// CHECK: sha1h s0, s1 // encoding: [0x20,0x08,0x28,0x5e]
|
||||
// CHECK: sha1su1 v0.4s, v1.4s // encoding: [0x20,0x18,0x28,0x5e]
|
||||
// CHECK: sha256su0 v0.4s, v1.4s // encoding: [0x20,0x28,0x28,0x5e]
|
||||
|
||||
sha1c q0, s1, v2.4s
|
||||
sha1p q0, s1, v2.4s
|
||||
sha1m q0, s1, v2.4s
|
||||
sha1su0 v0.4s, v1.4s, v2.4s
|
||||
sha256h q0, q1, v2.4s
|
||||
sha256h2 q0, q1, v2.4s
|
||||
sha256su1 v0.4s, v1.4s, v2.4s
|
||||
|
||||
// CHECK: sha1c q0, s1, v2.4s // encoding: [0x20,0x00,0x02,0x5e]
|
||||
// CHECK: sha1p q0, s1, v2.4s // encoding: [0x20,0x10,0x02,0x5e]
|
||||
// CHECK: sha1m q0, s1, v2.4s // encoding: [0x20,0x20,0x02,0x5e]
|
||||
// CHECK: sha1su0 v0.4s, v1.4s, v2.4s // encoding: [0x20,0x30,0x02,0x5e]
|
||||
// CHECK: sha256h q0, q1, v2.4s // encoding: [0x20,0x40,0x02,0x5e]
|
||||
// CHECK: sha256h2 q0, q1, v2.4s // encoding: [0x20,0x50,0x02,0x5e]
|
||||
// CHECK: sha256su1 v0.4s, v1.4s, v2.4s // encoding: [0x20,0x60,0x02,0x5e]
|
||||
|
||||
@ -5088,3 +5088,109 @@
|
||||
// CHECK-ERROR: error: invalid operand for instruction
|
||||
// CHECK-ERROR: ucvtf d21, s14, #64
|
||||
// CHECK-ERROR: ^
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Scalar Unsigned Saturating Extract Narrow
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
aese v0.8h, v1.8h
|
||||
aese v0.4s, v1.4s
|
||||
aese v0.2d, v1.2d
|
||||
aesd v0.8h, v1.8h
|
||||
aesmc v0.8h, v1.8h
|
||||
aesimc v0.8h, v1.8h
|
||||
|
||||
// CHECK: error: invalid operand for instruction
|
||||
// CHECK: aese v0.8h, v1.8h
|
||||
// CHECK: ^
|
||||
// CHECK: error: invalid operand for instruction
|
||||
// CHECK: aese v0.4s, v1.4s
|
||||
// CHECK: ^
|
||||
// CHECK: error: invalid operand for instruction
|
||||
// CHECK: aese v0.2d, v1.2d
|
||||
// CHECK: ^
|
||||
// CHECK: error: invalid operand for instruction
|
||||
// CHECK: aesd v0.8h, v1.8h
|
||||
// CHECK: ^
|
||||
// CHECK: error: invalid operand for instruction
|
||||
// CHECK: aesmc v0.8h, v1.8h
|
||||
// CHECK: ^
|
||||
// CHECK: error: invalid operand for instruction
|
||||
// CHECK: aesimc v0.8h, v1.8h
|
||||
// CHECK: ^
|
||||
|
||||
sha1h b0, b1
|
||||
sha1h h0, h1
|
||||
sha1h d0, d1
|
||||
sha1h q0, q1
|
||||
sha1su1 v0.16b, v1.16b
|
||||
sha1su1 v0.8h, v1.8h
|
||||
sha1su1 v0.2d, v1.2d
|
||||
sha256su0 v0.16b, v1.16b
|
||||
|
||||
// CHECK: error: invalid operand for instruction
|
||||
// CHECK: sha1h b0, b1
|
||||
// CHECK: ^
|
||||
// CHECK: error: invalid operand for instruction
|
||||
// CHECK: sha1h h0, h1
|
||||
// CHECK: ^
|
||||
// CHECK: error: invalid operand for instruction
|
||||
// CHECK: sha1h d0, d1
|
||||
// CHECK: ^
|
||||
// CHECK: error: invalid operand for instruction
|
||||
// CHECK: sha1h q0, q1
|
||||
// CHECK: ^
|
||||
// CHECK: error: invalid operand for instruction
|
||||
// CHECK: sha1su1 v0.16b, v1.16b
|
||||
// CHECK: ^
|
||||
// CHECK: error: invalid operand for instruction
|
||||
// CHECK: sha1su1 v0.8h, v1.8h
|
||||
// CHECK: ^
|
||||
// CHECK: error: invalid operand for instruction
|
||||
// CHECK: sha1su1 v0.2d, v1.2d
|
||||
// CHECK: ^
|
||||
// CHECK: error: invalid operand for instruction
|
||||
// CHECK: sha256su0 v0.16b, v1.16b
|
||||
// CHECK: ^
|
||||
|
||||
sha1c q0, q1, v2.4s
|
||||
sha1p q0, q1, v2.4s
|
||||
sha1m q0, q1, v2.4s
|
||||
sha1su0 v0.16b, v1.16b, v2.16b
|
||||
sha1su0 v0.8h, v1.8h, v2.8h
|
||||
sha1su0 v0.2d, v1.2d, v2.2d
|
||||
sha256h q0, q1, q2
|
||||
sha256h v0.4s, v1.4s, v2.4s
|
||||
sha256h2 q0, q1, q2
|
||||
sha256su1 v0.16b, v1.16b, v2.16b
|
||||
|
||||
// CHECK: error: invalid operand for instruction
|
||||
// CHECK: sha1c q0, q1, v2.4s
|
||||
// CHECK: ^
|
||||
// CHECK: error: invalid operand for instruction
|
||||
// CHECK: sha1p q0, q1, v2.4s
|
||||
// CHECK: ^
|
||||
// CHECK: error: invalid operand for instruction
|
||||
// CHECK: sha1m q0, q1, v2.4s
|
||||
// CHECK: ^
|
||||
// CHECK: error: invalid operand for instruction
|
||||
// CHECK: sha1su0 v0.16b, v1.16b, v2.16b
|
||||
// CHECK: ^
|
||||
// CHECK: error: invalid operand for instruction
|
||||
// CHECK: sha1su0 v0.8h, v1.8h, v2.8h
|
||||
// CHECK: ^
|
||||
// CHECK: error: invalid operand for instruction
|
||||
// CHECK: sha1su0 v0.2d, v1.2d, v2.2d
|
||||
// CHECK: ^
|
||||
// CHECK: error: too few operands for instruction
|
||||
// CHECK: sha256h q0, q1, q2
|
||||
// CHECK: ^
|
||||
// CHECK: error: invalid operand for instruction
|
||||
// CHECK: sha256h v0.4s, v1.4s, v2.4s
|
||||
// CHECK: ^
|
||||
// CHECK: error: too few operands for instruction
|
||||
// CHECK: sha256h2 q0, q1, q2
|
||||
// CHECK: ^
|
||||
// CHECK: error: invalid operand for instruction
|
||||
// CHECK: sha256su1 v0.16b, v1.16b, v2.16b
|
||||
// CHECK: ^
|
||||
|
||||
Loading…
Reference in New Issue
Block a user