6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-12 13:30:51 +00:00
Code Issues Projects Releases Wiki Activity

Fix SimplifyDemandedBits' AssertZext logic to demand all the bits. It

Browse Source 
needs to demand the high bits because it's asserting that they're zero.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105406 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2010-06-03 20:21:33 +00:00
parent 3844173f6e
commit 400f75cb5e
2 changed files with 30 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -1498,13 +1498,17 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
break;
}
case ISD::AssertZext: {
EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
APInt InMask = APInt::getLowBitsSet(BitWidth,
VT.getSizeInBits());
if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask,
// Demand all the bits of the input that are demanded in the output.
// The low bits are obvious; the high bits are demanded because we're
// asserting that they're zero here.
if (SimplifyDemandedBits(Op.getOperand(0), NewMask,
KnownZero, KnownOne, TLO, Depth+1))
return true;
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
APInt InMask = APInt::getLowBitsSet(BitWidth,
VT.getSizeInBits());
KnownZero |= ~InMask & NewMask;
break;
}

22
test/CodeGen/X86/promote-assert-zext.ll Normal file
View File

@ -0,0 +1,22 @@
; RUN: llc < %s | FileCheck %s
; rdar://8051990
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
target triple = "x86_64-apple-darwin11"
; ISel doesn't yet know how to eliminate this extra zero-extend. But until
; it knows how to do so safely, it shouldn;t eliminate it.
; CHECK: movzbl (%rdi), %eax
; CHECK: movzwl %ax, %eax
define i64 @_ZL5matchPKtPKhiR9MatchData(i8* %tmp13) nounwind {
entry:
%tmp14 = load i8* %tmp13, align 1
%tmp17 = zext i8 %tmp14 to i16
br label %bb341
bb341:
%tmp18 = add i16 %tmp17, -1
%tmp23 = sext i16 %tmp18 to i64
ret i64 %tmp23
}