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https://github.com/c64scene-ar/llvm-6502.git
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Fixing truncate. Previously we were emitting truncate from r16 to r8 as
movw. That is we promote the destination operand to r16. So %CH = TRUNC_R16_R8 %BP is emitted as movw %bp, %cx. This is incorrect. If %cl is live, it would be clobbered. Ideally we want to do the opposite, that is emitted it as movb ??, %ch But this is not possible since %bp does not have a r8 sub-register. We are now defining a new register class R16_ which is a subclass of R16 containing only those 16-bit registers that have r8 sub-registers (i.e. AX - DX). We isel the truncate to two instructions, a MOV16to16_ to copy the value to the R16_ class, followed by a TRUNC_R16_R8. Due to bug 770, the register colaescer is not going to coalesce between R16 and R16_. That will be fixed later so we can eliminate the MOV16to16_. Right now, it can only be eliminated if we are lucky that source and destination registers are the same. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28164 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -89,7 +89,7 @@ void X86IntelAsmPrinter::printOp(const MachineOperand &MO,
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unsigned Reg = MO.getReg();
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if (Modifier && strncmp(Modifier, "trunc", strlen("trunc")) == 0) {
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MVT::ValueType VT = (strcmp(Modifier,"trunc16") == 0)
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? MVT::i16 : MVT::i32;
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? MVT::i16 : MVT::i8;
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Reg = getX86SubSuperRegister(Reg, VT);
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}
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O << RI.get(Reg).Name;
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@@ -268,12 +268,13 @@ void X86IntelAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
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const MachineOperand &MO1 = MI->getOperand(1);
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unsigned Reg0 = MO0.getReg();
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unsigned Reg1 = MO1.getReg();
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if (MI->getOpcode() == X86::TRUNC_R16_R8)
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Reg0 = getX86SubSuperRegister(Reg0, MVT::i16);
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if (MI->getOpcode() == X86::TRUNC_R32_R16)
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Reg1 = getX86SubSuperRegister(Reg1, MVT::i16);
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else
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Reg0 = getX86SubSuperRegister(Reg0, MVT::i32);
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if (Reg0 == Reg1)
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O << CommentString << " TRUNCATE ";
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Reg1 = getX86SubSuperRegister(Reg1, MVT::i8);
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O << CommentString << " TRUNCATE ";
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if (Reg0 != Reg1)
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O << "\n\t";
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break;
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}
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}
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