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Fix 80-column violation and extraneous brackets.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146566 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier 2011-12-14 17:26:05 +00:00
parent 20536b5bca
commit 404ed3c223
1 changed files with 9 additions and 8 deletions
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17
lib/Target/ARM/ARMFastISel.cpp
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@ -178,8 +178,9 @@ class ARMFastISel : public FastISel {
bool isLoadTypeLegal(Type *Ty, MVT &VT);
bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
bool isZExt);
bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr, unsigned Alignment = 0,
bool isZExt = true, bool allocReg = true);
bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr,
unsigned Alignment = 0, bool isZExt = true,
bool allocReg = true);
bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr,
unsigned Alignment = 0);
@ -1027,11 +1028,11 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr,
}
break;
case MVT::f64:
if (Alignment && Alignment < 4) {
// FIXME: Unaligned loads need special handling. Doublewords require
// word-alignment.
// FIXME: Unaligned loads need special handling. Doublewords require
// word-alignment.
if (Alignment && Alignment < 4)
return false;
}
Opc = ARM::VLDRD;
RC = TLI.getRegClassFor(VT);
break;
@ -1145,9 +1146,9 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr,
if (!Subtarget->hasVFP2()) return false;
// FIXME: Unaligned stores need special handling. Doublewords require
// word-alignment.
if (Alignment && Alignment < 4) {
if (Alignment && Alignment < 4)
return false;
}
StrOpc = ARM::VSTRD;
break;
}