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- Style cleanup in IA64ISelLowering.h: add 'virtual' keyword for consistency.

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- Add test pattern matching in CellSPU's icmp32.ll test harness
- Fix CellSPU fcmp.ll-generated assert.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48197 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Scott Michel 2008-03-10 23:49:09 +00:00
parent 45f36ea448
commit 405fba12ce
3 changed files with 20 additions and 10 deletions
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16
lib/Target/CellSPU/SPUISelLowering.cpp
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@ -122,9 +122,6 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
setUseUnderscoreLongJmp(true);
// Set up the SPU's register classes:
// NOTE: i8 register class is not registered because we cannot determine when
// we need to zero or sign extend for custom-lowered loads and stores.
// NOTE: Ignore the previous note. For now. :-)
addRegisterClass(MVT::i8, SPU::R8CRegisterClass);
addRegisterClass(MVT::i16, SPU::R16CRegisterClass);
addRegisterClass(MVT::i32, SPU::R32CRegisterClass);
@ -243,22 +240,19 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
setOperationAction(ISD::CTLZ , MVT::i32, Legal);
// SPU has a version of select
// SPU has a version of select that implements (a&~c)|(b|c), just like
// select ought to work:
setOperationAction(ISD::SELECT, MVT::i1, Promote);
setOperationAction(ISD::SELECT, MVT::i8, Legal);
setOperationAction(ISD::SELECT, MVT::i16, Legal);
setOperationAction(ISD::SELECT, MVT::i32, Legal);
setOperationAction(ISD::SELECT, MVT::i64, Expand);
setOperationAction(ISD::SELECT, MVT::f32, Expand);
setOperationAction(ISD::SELECT, MVT::f64, Expand);
setOperationAction(ISD::SETCC, MVT::i1, Promote);
setOperationAction(ISD::SETCC, MVT::i8, Legal);
setOperationAction(ISD::SETCC, MVT::i16, Legal);
setOperationAction(ISD::SETCC, MVT::i32, Legal);
setOperationAction(ISD::SETCC, MVT::i64, Expand);
setOperationAction(ISD::SETCC, MVT::f32, Expand);
setOperationAction(ISD::SETCC, MVT::f64, Expand);
// Zero extension and sign extension for i64 have to be
// custom legalized
@ -449,7 +443,11 @@ SPUTargetLowering::getTargetNodeName(unsigned Opcode) const
MVT::ValueType
SPUTargetLowering::getSetCCResultType(const SDOperand &Op) const {
return Op.getValueType();
MVT::ValueType VT = Op.getValueType();
if (MVT::isInteger(VT))
return VT;
else
return MVT::i32;
}
//===----------------------------------------------------------------------===//

4
lib/Target/IA64/IA64ISelLowering.h
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@ -47,7 +47,9 @@ namespace llvm {
unsigned VirtGPR; // this is public so it can be accessed in the selector
// for ISD::RET. add an accessor instead? FIXME
const char *getTargetNodeName(unsigned Opcode) const;
MVT::ValueType getSetCCResultType(const SDOperand &) const;
/// getSetCCResultType: return ISD::SETCC's result type.
virtual MVT::ValueType getSetCCResultType(const SDOperand &) const;
/// LowerArguments - This hook must be implemented to indicate how we should
/// lower the arguments for the specified function, into the specified DAG.

10
test/CodeGen/CellSPU/icmp32.ll
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@ -1,4 +1,14 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: grep ila %t1.s | count 6
; RUN: grep ceq %t1.s | count 28
; RUN: grep ceqi %t1.s | count 11
; RUN: grep clgt %t1.s | count 16
; RUN: grep clgti %t1.s | count 5
; RUN: grep cgt %t1.s | count 16
; RUN: grep cgti %t1.s | count 6
; RUN: grep {selb\t\\\$3, \\\$6, \\\$5, \\\$3} %t1.s | count 7
; RUN: grep {selb\t\\\$3, \\\$5, \\\$6, \\\$3} %t1.s | count 3
; RUN: grep {selb\t\\\$3, \\\$5, \\\$4, \\\$3} %t1.s | count 20
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
target triple = "spu"