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[mips] Fix FP conditional move instructions to have explicit FP condition code
register operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187242 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -34,20 +34,18 @@ class CMov_I_F_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC,
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// cond:float, data:int
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// cond:float, data:int
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class CMov_F_I_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
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class CMov_F_I_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
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SDPatternOperator OpNode = null_frag> :
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SDPatternOperator OpNode = null_frag> :
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InstSE<(outs RC:$rd), (ins RC:$rs, RC:$F),
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InstSE<(outs RC:$rd), (ins RC:$rs, FCC:$fcc, RC:$F),
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!strconcat(opstr, "\t$rd, $rs, $$fcc0"),
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!strconcat(opstr, "\t$rd, $rs, $fcc"),
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[(set RC:$rd, (OpNode RC:$rs, RC:$F))], Itin, FrmFR> {
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[(set RC:$rd, (OpNode RC:$rs, FCC:$fcc, RC:$F))], Itin, FrmFR> {
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let Uses = [FCC0];
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let Constraints = "$F = $rd";
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let Constraints = "$F = $rd";
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}
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}
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// cond:float, data:float
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// cond:float, data:float
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class CMov_F_F_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
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class CMov_F_F_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
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SDPatternOperator OpNode = null_frag> :
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SDPatternOperator OpNode = null_frag> :
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InstSE<(outs RC:$fd), (ins RC:$fs, RC:$F),
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InstSE<(outs RC:$fd), (ins RC:$fs, FCC:$fcc, RC:$F),
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!strconcat(opstr, "\t$fd, $fs, $$fcc0"),
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!strconcat(opstr, "\t$fd, $fs, $fcc"),
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[(set RC:$fd, (OpNode RC:$fs, RC:$F))], Itin, FrmFR> {
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[(set RC:$fd, (OpNode RC:$fs, FCC:$fcc, RC:$F))], Itin, FrmFR> {
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let Uses = [FCC0];
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let Constraints = "$F = $fd";
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let Constraints = "$F = $fd";
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}
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}
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@ -519,9 +519,10 @@ static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
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SDValue False, SDLoc DL) {
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SDValue False, SDLoc DL) {
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ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
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ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
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bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
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bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
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SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
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return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
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return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
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True.getValueType(), True, False, Cond);
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True.getValueType(), True, FCC0, False, Cond);
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}
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}
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static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
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static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
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@ -29,8 +29,8 @@ def SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisInt<0>,
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SDTCisVT<2, OtherVT>]>;
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SDTCisVT<2, OtherVT>]>;
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def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>,
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def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>,
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SDTCisVT<2, i32>]>;
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SDTCisVT<2, i32>]>;
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def SDT_MipsCMovFP : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
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def SDT_MipsCMovFP : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisVT<2, i32>,
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SDTCisSameAs<1, 2>]>;
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SDTCisSameAs<1, 3>]>;
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def SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>;
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def SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>;
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def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
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def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
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SDTCisVT<1, i32>,
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SDTCisVT<1, i32>,
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@ -716,12 +716,13 @@ class CMov_I_F_FM<bits<6> funct, bits<5> fmt> {
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class CMov_F_I_FM<bit tf> {
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class CMov_F_I_FM<bit tf> {
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bits<5> rd;
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bits<5> rd;
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bits<5> rs;
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bits<5> rs;
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bits<3> fcc;
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bits<32> Inst;
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bits<32> Inst;
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let Inst{31-26} = 0;
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let Inst{31-26} = 0;
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let Inst{25-21} = rs;
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let Inst{25-21} = rs;
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let Inst{20-18} = 0; // cc
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let Inst{20-18} = fcc;
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let Inst{17} = 0;
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let Inst{17} = 0;
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let Inst{16} = tf;
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let Inst{16} = tf;
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let Inst{15-11} = rd;
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let Inst{15-11} = rd;
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@ -732,12 +733,13 @@ class CMov_F_I_FM<bit tf> {
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class CMov_F_F_FM<bits<5> fmt, bit tf> {
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class CMov_F_F_FM<bits<5> fmt, bit tf> {
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bits<5> fd;
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bits<5> fd;
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bits<5> fs;
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bits<5> fs;
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bits<3> fcc;
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bits<32> Inst;
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bits<32> Inst;
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let Inst{31-26} = 0x11;
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let Inst{31-26} = 0x11;
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let Inst{25-21} = fmt;
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let Inst{25-21} = fmt;
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let Inst{20-18} = 0; // cc
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let Inst{20-18} = fcc;
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let Inst{17} = 0;
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let Inst{17} = 0;
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let Inst{16} = tf;
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let Inst{16} = tf;
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let Inst{15-11} = fs;
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let Inst{15-11} = fs;
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@ -266,6 +266,24 @@
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# CHECK: mov.s $f6, $f7
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# CHECK: mov.s $f6, $f7
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0x46 0x00 0x39 0x86
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0x46 0x00 0x39 0x86
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# CHECK: movf $3, $2, $fcc7
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0x00,0x5c,0x18,0x01
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# CHECK: movf.d $f4, $f2, $fcc7
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0x46,0x3c,0x11,0x11
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# CHECK: movf.s $f4, $f2, $fcc7
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0x46,0x1c,0x11,0x11
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# CHECK: movt $3, $2, $fcc7
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0x00,0x5d,0x18,0x01
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# CHECK: movt.d $f4, $f2, $fcc7
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0x46,0x3d,0x11,0x11
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# CHECK: movt.s $f4, $f2, $fcc7
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0x46,0x1d,0x11,0x11
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# CHECK: msub $6, $7
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# CHECK: msub $6, $7
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0x70 0xc7 0x00 0x04
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0x70 0xc7 0x00 0x04
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@ -272,6 +272,24 @@
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# CHECK: move $3, $2
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# CHECK: move $3, $2
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0x25,0x18,0x40,0x00
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0x25,0x18,0x40,0x00
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# CHECK: movf $3, $2, $fcc7
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0x01,0x18,0x5c,0x00
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# CHECK: movf.d $f4, $f2, $fcc7
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0x11,0x11,0x3c,0x46
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# CHECK: movf.s $f4, $f2, $fcc7
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0x11,0x11,0x1c,0x46
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# CHECK: movt $3, $2, $fcc7
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0x01,0x18,0x5d,0x00
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# CHECK: movt.d $f4, $f2, $fcc7
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0x11,0x11,0x3d,0x46
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# CHECK: movt.s $f4, $f2, $fcc7
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0x11,0x11,0x1d,0x46
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# CHECK: msub $6, $7
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# CHECK: msub $6, $7
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0x04 0x00 0xc7 0x70
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0x04 0x00 0xc7 0x70
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