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[mips] Fix FP conditional move instructions to have explicit FP condition code

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register operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187242 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2013-07-26 20:51:20 +00:00
parent 8b68480453
commit 407883b69b
6 changed files with 50 additions and 13 deletions
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14
lib/Target/Mips/MipsCondMov.td
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@ -34,20 +34,18 @@ class CMov_I_F_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC,
// cond:float, data:int
class CMov_F_I_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
SDPatternOperator OpNode = null_frag> :
InstSE<(outs RC:$rd), (ins RC:$rs, RC:$F),
!strconcat(opstr, "\t$rd, $rs, $$fcc0"),
[(set RC:$rd, (OpNode RC:$rs, RC:$F))], Itin, FrmFR> {
let Uses = [FCC0];
InstSE<(outs RC:$rd), (ins RC:$rs, FCC:$fcc, RC:$F),
!strconcat(opstr, "\t$rd, $rs, $fcc"),
[(set RC:$rd, (OpNode RC:$rs, FCC:$fcc, RC:$F))], Itin, FrmFR> {
let Constraints = "$F = $rd";
}
// cond:float, data:float
class CMov_F_F_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
SDPatternOperator OpNode = null_frag> :
InstSE<(outs RC:$fd), (ins RC:$fs, RC:$F),
!strconcat(opstr, "\t$fd, $fs, $$fcc0"),
[(set RC:$fd, (OpNode RC:$fs, RC:$F))], Itin, FrmFR> {
let Uses = [FCC0];
InstSE<(outs RC:$fd), (ins RC:$fs, FCC:$fcc, RC:$F),
!strconcat(opstr, "\t$fd, $fs, $fcc"),
[(set RC:$fd, (OpNode RC:$fs, FCC:$fcc, RC:$F))], Itin, FrmFR> {
let Constraints = "$F = $fd";
}

3
lib/Target/Mips/MipsISelLowering.cpp
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@ -519,9 +519,10 @@ static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
SDValue False, SDLoc DL) {
ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
True.getValueType(), True, False, Cond);
True.getValueType(), True, FCC0, False, Cond);
}
static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,

4
lib/Target/Mips/MipsInstrFPU.td
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@ -29,8 +29,8 @@ def SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisInt<0>,
SDTCisVT<2, OtherVT>]>;
def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>,
SDTCisVT<2, i32>]>;
def SDT_MipsCMovFP : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
SDTCisSameAs<1, 2>]>;
def SDT_MipsCMovFP : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisVT<2, i32>,
SDTCisSameAs<1, 3>]>;
def SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>;
def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
SDTCisVT<1, i32>,

6
lib/Target/Mips/MipsInstrFormats.td
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@ -716,12 +716,13 @@ class CMov_I_F_FM<bits<6> funct, bits<5> fmt> {
class CMov_F_I_FM<bit tf> {
bits<5> rd;
bits<5> rs;
bits<3> fcc;
bits<32> Inst;
let Inst{31-26} = 0;
let Inst{25-21} = rs;
let Inst{20-18} = 0; // cc
let Inst{20-18} = fcc;
let Inst{17} = 0;
let Inst{16} = tf;
let Inst{15-11} = rd;
@ -732,12 +733,13 @@ class CMov_F_I_FM<bit tf> {
class CMov_F_F_FM<bits<5> fmt, bit tf> {
bits<5> fd;
bits<5> fs;
bits<3> fcc;
bits<32> Inst;
let Inst{31-26} = 0x11;
let Inst{25-21} = fmt;
let Inst{20-18} = 0; // cc
let Inst{20-18} = fcc;
let Inst{17} = 0;
let Inst{16} = tf;
let Inst{15-11} = fs;

18
test/MC/Disassembler/Mips/mips32.txt
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@ -266,6 +266,24 @@
# CHECK: mov.s $f6, $f7
0x46 0x00 0x39 0x86
# CHECK: movf $3, $2, $fcc7
0x00,0x5c,0x18,0x01
# CHECK: movf.d $f4, $f2, $fcc7
0x46,0x3c,0x11,0x11
# CHECK: movf.s $f4, $f2, $fcc7
0x46,0x1c,0x11,0x11
# CHECK: movt $3, $2, $fcc7
0x00,0x5d,0x18,0x01
# CHECK: movt.d $f4, $f2, $fcc7
0x46,0x3d,0x11,0x11
# CHECK: movt.s $f4, $f2, $fcc7
0x46,0x1d,0x11,0x11
# CHECK: msub $6, $7
0x70 0xc7 0x00 0x04

18
test/MC/Disassembler/Mips/mips32_le.txt
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@ -272,6 +272,24 @@
# CHECK: move $3, $2
0x25,0x18,0x40,0x00
# CHECK: movf $3, $2, $fcc7
0x01,0x18,0x5c,0x00
# CHECK: movf.d $f4, $f2, $fcc7
0x11,0x11,0x3c,0x46
# CHECK: movf.s $f4, $f2, $fcc7
0x11,0x11,0x1c,0x46
# CHECK: movt $3, $2, $fcc7
0x01,0x18,0x5d,0x00
# CHECK: movt.d $f4, $f2, $fcc7
0x11,0x11,0x3d,0x46
# CHECK: movt.s $f4, $f2, $fcc7
0x11,0x11,0x1d,0x46
# CHECK: msub $6, $7
0x04 0x00 0xc7 0x70